QCA memory with parallel read/serial write: design and analysis

QCA memory with parallel read/serial write: design and analysis

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IEE Proceedings - Circuits, Devices and Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors present a novel memory architecture for quantum-dot cellular automata (QCA). The proposed architecture combines the advantage of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory, hence its name is ‘hybrid’. This hybrid architecture utilises a novel arrangement in the addressing circuitry of the QCA loop for implementing the memory-in-motion paradigm. An evaluation of latency and area is pursued. It is shown that while for a serial memory, latency is O(N) (where N is the number of bits in a loop), a constant latency is accomplished in the hybrid memory. For area analysis, a novel characterisation that considers cells in the logic circuitry, interconnect in addition to the unused portion of the Cartesian plane (i.e. the whole geometric area encompassing the QCA layout), is proposed. This is referred to as the effective area. Different layouts of the hybrid memory are proposed to substantiate the reduction in effective area.


    1. 1)
      • Lent, C.S., Tougaw, P.D., Porod, W.: `Quantum cellular automata: the physics of computing with arrays of quantum dot molecules', PhysComp 94: Proc. Workshop on Physics and Computing, 1994, IEEE Computer Society Press.
    2. 2)
    3. 3)
    4. 4)
      • Compano, R., Molenkamp, L., Paul, D.J.: ‘Technology roadmap for nanoelectroincs’, in European Commission IST programme, Future and Emerging Technologies.
    5. 5)
      • Niemier, M.T., Kogge, P.M.: `Logic in wire: using quantum dots to implement a microprocessor', Int. Conf. on Electronics, Circuits, and Systems (ICECS ’99), September 1999, Cyprus.
    6. 6)
    7. 7)
      • Niemier, M.T., Rodrigues, A.F., Kogge, P.M.: `A potentially implementable FPGA for quantum dot cellular automata', Workshop on Non-Silicon Computation (NSC-1), 2002, Boston, MA, USA.
    8. 8)
      • Frost, S.E., Rodrigues, A.F., Janiszewski, A.W., Rausch, R.T., Kogge, P.M.: `Memory in motion: a study of storage structures in QCA', First Workshop on Non-Silicon Computing, 2002, 2.
    9. 9)
      • Tougaw, P.D., Lent, C.S.: `A potentially implementable FPGA for quantum dot cellular automata', Workshop on Non-Silicon Computation (NSC-1), 1994, Boston, MA.
    10. 10)
      • Dimitrov, V.S., Jullien, G.A., Walus, K.: `Quantum-dot cellular automata carry-look-ahead adder and barrel shifter', IEEE Emerging Telecommunications Technologies Conf., 2002.
    11. 11)
      • Walus, K., Vetteth, A., Jullien, G.A., Dimitrov, V.S.: `RAM design using quantum-dot cellular automata', Technical Proc. 2003 Nanotechnology Conf. and Trade Show, March 2003, 2, p. 160–163.
    12. 12)
    13. 13)
      • M.T. Niemier , P.M. Kogge . Problems in designing with QCAS: layout=timing. Int. J. Circuit Theory Appl. , 1 , 49 - 62
    14. 14)
      • Berzon, T.J., Fountain, D.: `A memory design in QCAS using the squares formalism', Proc. Ninth Great Lakes Symp. VLSI ’00, March 1999, p. 166–169.
    15. 15)
      • Ottavi, M., Pontarelli, S., Vankamamidi, V., Lombardi, F.: `Design of a QCA memory with parallel read/serial write', Proc. IEEE Computer Society Ann. Symp. on VLSI, May 2005, p. 292–294.
    16. 16)
      • Blair, E.P., Lent, C.S.: `Quantum-dot cellular automata: an architecture for molecular computing', Int. Conf. on Simulation of Semiconductor Processes and Devices SISPAD 2003, Sept. 2003, 2, p. 14–18.
    17. 17)
      • ‘International Technology roadmap’, 2003,
    18. 18)

Related content

This is a required field
Please enter a valid email address