© The Institution of Engineering and Technology
A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures.
References
-
-
1)
-
S. Liu ,
C. Chang
.
CMOS subthreshold four quadrant multiplier based on unbalanced source coupled pairs.
Int. J. Electron
,
327 -
332
-
2)
-
G. Han ,
E. Sanchez-Sinencio
.
CMOS transconductance multipliers: A tutorial.
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
,
12 ,
1550 -
1563
-
3)
-
S. Liu ,
Y. Hwang
.
CMOC four-quadrant multiplier using bias feedback techniques.
IEEE J. Solid-State Circuits
,
750 -
752
-
4)
-
Z. Czarnul
.
Novel MOS resistive circuit for synthesis of fully-integrated continuous-time filters.
IEEE Trans. Circuits Syst.
,
718 -
721
-
5)
-
Maundy, B., Aronhime, P.: `Useful multipliers for low-voltage applications', Proc. IEEE International Symposium on Circuits and Systems, May 2002, 1, p. 26–29.
-
6)
-
Li, G., Maundy, B.: `A novel quadrant CMOS analog multiplier/divider', Proc. Int. Symp. on Circuits and Systems, May 2004, 1, p. 1108–1111.
-
7)
-
Mehrvarz, H.R., Kwok, C.Y.: `A large-input-dynamic-range multi-input floating gate MOS four-quadrant analog multiplier', Proc. IEEE Int. Solid-State Conf., February 1995, p. 60–61.
-
8)
-
Z. Wang
.
A four-transistor four-quadrant analog multiplier using MOS transistors operating in the saturation region.
IEEE Trans. Instrum. Meas.
,
1 ,
75 -
77
-
9)
-
Ramirez-Augulo, J., Thoutam, S., Lopez-Martin, A., Carvajal, R.J.: `Low-voltage CMOS analog four quadrant multiplier based on flipped voltage followers', Proc. Int. Symp. on Circuits and Systems, May 2004, 1, p. 681–684.
-
10)
-
S.T. Lee ,
K.T. Lau ,
L. Siek
.
Four-quadrant CMOS analogue multiplier for artificial neural networks.
Electron. Lett.
,
48 -
49
-
11)
-
J.N. Babanezhad ,
G.C. Temes
.
A 20-V four-quadrant CMOS analog multiplier.
IEEE J. Solid-State Circuits
,
1158 -
1168
-
12)
-
B. Razavi
.
(2002)
Design of analog CMOS integrated circuits.
-
13)
-
Changyue, O., Peng, C., Yizhong, X.: `Study of switched capacitor multiplier', Proc. Int. Conf. Circuits and Systems, June 1991, China, p. 234–237.
-
14)
-
U. Gatti ,
F. Maloberti ,
G. Torelli
.
CMOS triode-transistor transconductor for high-frequency continuous-time filters.
IEE Proc., Circuits Devices Syst.
,
6 ,
462 -
468
-
15)
-
Maundy, B., Aronhime, P.: `Useful multipliers for low-voltage applications', Proc. Int. Symp. on Circuits and Systems, May 2002, 1, p. 737–740.
-
16)
-
K. Bult ,
H. Wallinga
.
A four-quadrant analog multiplier.
IEEE J. Solid-State Circuits
,
3 ,
430 -
435
-
17)
-
B. Gibert
.
A precision four-quadrant multiplier with subnanosecond response.
IEEE J. Solid-State- Circuits
,
353 -
365
-
18)
-
S.I. Liu
.
Low voltage CMOS four-quadrant multiplier.
Electron. Lett.
,
2125 -
2126
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