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A low-power low-noise CMOS analogue multiplier

A low-power low-noise CMOS analogue multiplier

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A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures.

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