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Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders

Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders

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© The Institution of Engineering and Technology
Published

Novel methods for implementing low-power hardware and configurable architectures comprising several different kinds of shift registers in field programmable gate arrays are presented. New approaches are also described to reduce the power dissipation of shift register structures without compromising their configurability. The proposed structures are particularly effective to reduce the power dissipation of shift registers of medium and large lengths. A systematic method to select the best shift register structure is also provided. The proposed structures and the selection method are generic, and they can be configured statically or dynamically. It is shown that they are well suited for implementing powerful convolutional encoders and suitable decoders associated with forward error correction techniques such as iterative threshold decoding.

Inspec keywords: convolutional codes; iterative decoding; low-power electronics; shift registers; error correction codes; field programmable gate arrays

Other keywords: field programmable gate arrays; low power configurable shift register; convolutional encoders; generic shift register; power dissipation; forward error correction; convolutional decoders; iterative threshold decoding; hardware realisations

Subjects: Logic and switching circuits; Codes; Logic circuits

References

    1. 1)
    2. 2)
      • Xilinx, http://www.xilinx.com/cgi-bin/powerweb.pl.
    3. 3)
      • Xilinx, Creating Efficient Multi-Tap Shift Registers, Quarterly Journal for Xilinx Programmable Logic Users Xcell 31, First Quarter, 1999, pp. 9–10, http://www.xilinx.com/xcell/xl31/xl31_9.pdf.
    4. 4)
      • Alfke, P.: Efficient shift registers, LFSR counters, and long pseudo-random sequence generators, Xapp052 (Version 1.1) July 7, 1996.
    5. 5)
      • Cardinal, C.: `Décodage à seuil itératif sans entrelacement des codes convolutionnels doublement orthogonaux', 2001, Ph.D., École Polytechnique de Montréal.
    6. 6)
      • A. Chandrakasan . (1997) Basics of low power circuit and logic design tutorial presented at École polytechnique Fédérale de Lausanne, Switzerland.
    7. 7)
      • Xilinx, Packaging Thermal Management, XAPP415 (v1.3) August 21, 2003, http://www.itc-electronics.com/CD/Xilinx%2010064/Datasource%200302%20V_7%202002/appnotes%xapp415.pdf.
    8. 8)
      • M. Lowy . Parallel implementation of linear feedback shift registers for low power applications. IEEE Trans. Circuits Syst. I, Analog Digit. Signal Process. , 6 , 458 - 466
    9. 9)
      • George, M., and Alfke, P.: ‘Linear feedback shift registers in virtex devices’, XAPP210 (v1.2) January 9, 2001.
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