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Quantitative method for evaluating quality of analogue VLSI layout

Quantitative method for evaluating quality of analogue VLSI layout

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A quantitative benchmarking metric is presented for the evaluation of the quality of analogue layout. It facilitates comparisons between alternative design automation tools and, for a given tool, provides assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net routing optimality. The algorithm has been developed to accommodate hierarchical structures, as well as flat designs. The metric allows the designer to alter the relative importance of area and routing efficiencies, although a recommendation is given on the appropriate balance. The results demonstrate the use of the metric to evaluate an automatic layout tool, and its effectiveness in providing a characterisation that corresponds to the expert designer's judgement.

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