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Set of self-timed latches for high-speed VLSI

Set of self-timed latches for high-speed VLSI

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A set of novel self-timed latches is introduced and analysed. These latches have no back-to-back connection as in conventional self-timed latches, and both inverting and noninverting outputs are evaluated simultaneously leading to higher operating frequencies. A novel type of cross-coupled inverter used in the proposed circuits implements static operation without the signal fighting with the main driver during signal transition. The power consumption of these latches is also comparable to, or less than, that of conventional circuits. The proposed latches are designed using a 0.35 µm CMOS technology. The comparison results indicate that the proposed active-low self-timed latch (ALSTL) improves speed by 22–34% over the conventional NAND SR latch, while for the active-high self-timed latch (AHSTL) the speed improvements are 20–35% with less power as compared to the corresponding NOR SR latch.

Inspec keywords: integrated circuit design; flip-flops; CMOS logic circuits; high-speed integrated circuits; VLSI; logic gates; logic CAD

Other keywords: operating frequencies; signal transition; active-low self-timed latch; static operation; active-high self-timed latch; CMOS technology; noninverting outputs; cross-coupled inverter; high-speed VLSI; self-timed latches; inverting outputs

Subjects: Logic and switching circuits; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Computer-aided circuit analysis and design; Electronic engineering computing; Computer-aided logic design; Logic circuits; Digital circuit design, modelling and testing

References

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      • Heller, L.G., Griffin, W.R., Davis, J.W., Thoma, N.G.: `Cascode voltage switch logic: a differential CMOS logic family', ISSCC digest technical papers, 1984, San Franscisco, USA, p. 16–17.
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