New current conveyor for high-speed low-power current sensing

Access Full Text

New current conveyor for high-speed low-power current sensing

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings - Circuits, Devices and Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A novel low-voltage current conveyor for fast CMOS SRAM applications is presented. The sensing speed is independent of the bit-line capacitances and a positive feedback technique is employed to give the circuit a high-speed and low-power operation. Performance evaluation has shown that, based on equal area ratios, the new conveyor outperforms the conventional circuit in terms of speed and average power dissipation by at least 30%. The static behaviour of the basic circuit is analysed, and HSPICE simulations have been used to characterise the circuits. Experimental results have verified the functionality of the new circuit and its superiority over the conventional CMOS current conveyor.

Inspec keywords: current conveyors; SPICE; circuit feedback; CMOS memory circuits; SRAM chips; circuit analysis computing

Other keywords: equal area ratios; sensing speed; low-power current sensing; current conveyor; average power dissipation; positive feedback technique; CMOS SRAM applications; static behaviour

Subjects: CMOS integrated circuits; Electronic engineering computing; Semiconductor storage; Computer-aided circuit analysis and design; Active filters and other active networks; Memory circuits

References

    1. 1)
      • Y.K. Seng , S.S. Rofail . A 1.1 V full-swing doublebootstrapped BiCMOS logic gates. IEE Proc. Circuits Devices Syst. , 1 , 41 - 45
    2. 2)
      • K.S. Yeo , S.S. Rofail . A full-swing high speed CBiCMOS digital circuit for low-voltage applications. IEE Proc. Circuits Devices Syst. , 1 , 8 - 14
    3. 3)
      • S.S. Rofail , K.S. Yeo . New complementary BiCMOS digital gates forlow-voltage environments. Solid-State Electron. , 5 , 681 - 687
    4. 4)
      • M. Takada , K. Nakamura , T. Yamazaki . High speed submicron BiCMOS memory. IEEE J. Solid-State Circuits , 3 , 497 - 505
    5. 5)
      • N. Weste , K. Eshraghian . (1985) Principles of CMOS VLSI design, a system perspective.
    6. 6)
      • K.Y. Toh , P.K. Ko , R.G. Meyer . An engineering model for short-channel MOS devices. IEEE J. Solid-State Circuits , 4 , 950 - 958
    7. 7)
      • E. Seevinck , P.J.V. Beers , H. Ontrop . Current-mode techniques for high-speed VLSI circuits with applicationto current senseamplifier for CMOS SRAM's. IEEE J. Solid-State Circuits , 5 , 525 - 536
    8. 8)
      • A.S. Shubat , R. Kazerounian , R. Irani , A. Roy , G.A. Rezvani , B. Eitan , C.Y. Yang . A bipolar load CMOS SRAM cell for embedded applications. IEEE Electron Device Lett. , 5 , 169 - 171
    9. 9)
      • N. Shibata . Current sense amplifiers for low-voltage memories. IEICE Trans. Electron. , 8 , 1120 - 1130
    10. 10)
      • D.A. Pucknell , K. Eshraghian . (1988) Basic VLSI design systemand circuit.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cds_19981601
Loading

Related content

content/journals/10.1049/ip-cds_19981601
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading