Sparsematrix solution is a dominant part of execution time in simulating VLSI circuits by a detailed simulation program such as SPICE. The paper develops a parallelblock partitionable sparsematrixsolution algorithm which exploits sparsity at the matrix block level as well as within a nonzero block. An efficient mapping scheme to assign different matrix blocks to processors is developed which maximises concurrency and minimises communication between processors. Associated reordering and efficient sparse storage schemes are also developed. Implementation of this parallel algorithm is carried out on a transputer processor array which plugs into a PC bus. The sparse matrix solver is tested on matrices generated from a transistorlevel expansion of ISCAS85 benchmark logic circuits. Good acceleration is obtained for all benchmark matrices up to the number of transputers available.
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