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Parallel sparse-matrix solution for direct circuit simulation on a transputer array

Parallel sparse-matrix solution for direct circuit simulation on a transputer array

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Sparse-matrix solution is a dominant part of execution time in simulating VLSI circuits by a detailed simulation program such as SPICE. The paper develops a parallel-block partitionable sparse-matrix-solution algorithm which exploits sparsity at the matrix block level as well as within a nonzero block. An efficient mapping scheme to assign different matrix blocks to processors is developed which maximises concurrency and minimises communication between processors. Associated reordering and efficient sparse storage schemes are also developed. Implementation of this parallel algorithm is carried out on a transputer processor array which plugs into a PC bus. The sparse matrix solver is tested on matrices generated from a transistor-level expansion of ISCAS-85 benchmark logic circuits. Good acceleration is obtained for all benchmark matrices up to the number of transputers available.

Inspec keywords: SPICE; VLSI; parallel algorithms; transputer systems; digital simulation; sparse matrices; circuit analysis computing

Other keywords: parallel sparse-matrix solution; concurrency; sparse storage schemes; SPICE; parallel-block partitionable solution algorithm; VLSI circuits; nonzero block; direct circuit simulation; matrix block level; transputer processor array; simulation program; transputer array; mapping scheme; reordering schemes; ISCAS-85 benchmark logic circuits

Subjects: Computer-aided circuit analysis and design; Electronic engineering computing; Algebra; Simulation techniques; Algebra; Algebra; Semiconductor integrated circuits

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