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Differential register bank design for self timed differential bipolar technology

Differential register bank design for self timed differential bipolar technology

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A high performance differential bipolar datapath based on the ARM architecture has been designed using ‘micropipeline’ self-timed techniques. The datapath design included a full-custom 31 × 32 bit register bank. Traditional bipolar single-ended design techniques are not suited to implementing a RAM of this size on the target technology. This has led to the adoption of a fully differential circuit for the RAM cell here. The paper describes the challenges of designing such a differential register bank and the surrounding self-timed control. The data path has been fabricated by GEC Plessey Semiconductors and is fully operational. Results for the register bank are presented in terms of speed, power consumption and area.

Inspec keywords: bipolar digital integrated circuits; asynchronous circuits; microprocessor chips; bipolar memory circuits; current-mode logic; random-access storage; bipolar logic circuits; timing; pipeline processing

Other keywords: differential register bank design; ALU; self timed differential bipolar technology; differential register bank; CML; micropipeline self-timed techniques; bipolar datapath; RAM cell; ARM architecture; full-custom register bank; GEC Plessey Semiconductors; self-timed control; fully differential circuit

Subjects: Memory circuits; Logic circuits; Semiconductor storage; Microprocessors and microcomputers; Microprocessor chips; Logic and switching circuits; Bipolar integrated circuits

References

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      • Furber, S.B., Day, P., Garside, J.D., Paver, N.C., Woods, J.V.: `AMULET1: A micropipelined ARM', Proceedings of IEEE computer conference (Compcon'94), March 1994, San Francisco, USA, p. 476–485.
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      • GEC Plessey Semiconductors, , : `Differential logic design manual (FAB 4)', July 1988, 1.0 Edition.
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