Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts; a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.
References
-
-
1)
-
Marinescu, M.: `Simple and efficient algorithms for functional RAM testing', Proceedings of IEEE international Test conference, 1982, p. 236–239.
-
2)
-
van de Goor, A.J.: Private communication with several memorymanufacturers(Digital, Intel, and Samsung). 1996.
-
3)
-
B. Nadeau-Dostie ,
A. Silbert ,
V.K. Agarwal
.
Serial interfacing for embedded memories.
IEEE Des. Test
,
2 ,
52 -
63
-
4)
-
C.A. Papachristou ,
N.B. Saghal
.
An improved method for detecting functional faults in random-accessmemories.
IEEE Trans. Comp. (USA)
,
2 ,
110 -
116
-
5)
-
A.J. van de Goor
.
Using march tests to test SRAMs.
IEEE Des. Test Comp.
,
8 -
14
-
6)
-
van de Goor, A.J., Gaydadjiev, G.N., Yarmolik, V.N., Mikitjuk, V.G.: `March LR: a test for realistic linked faults', Proceedings of 14th IEEE VLSI Test symposium, 1996, p. 272–280.
-
7)
-
A.J. van de Goor
.
(1998)
Testing semiconductor memories, theory and practice.
-
8)
-
D.S. Suk ,
S.M. Reddy
.
A march test for functional faults in semiconductor random-access memories.
IEEE Trans. Comp. (USA)
,
12 ,
982 -
985
-
9)
-
R. Dekker ,
F. Beenker ,
L. Thijssen
.
A realistic fault model and test algorithms for static random accessmemories.
IEEE Trans. Comp. (USA)
,
6 ,
567 -
572
-
10)
-
van de Goor, A.J., Smit, B.: `Generating march tests automatically', Proceedings international Test conference, 1994, p. 870–878.
-
11)
-
A.J. van de Goor ,
C.A. Verruijt
.
An overview of deterministic functional RAM chip testing.
ACM Comput. Surv.
,
1 ,
5 -
33
-
12)
-
J.H. de Jonge ,
A.J. Smeulders
.
Moving inversions test pattern is thorough, yet speedy.
Computer Des. (USA)
,
169 -
173
-
13)
-
P.K. Veenstra ,
F.P.M. Beenker ,
J.J.M. Koomen
.
Testing of random access memories: theory and practice.
IEE Proc. G
,
1 ,
24 -
28
-
14)
-
Dekker, R., Beenker, F., Thijssen, L.: `Fault modeling and test algorithm development for static randomaccess memories', Proceedings of IEEE international Test conference, 1988, Washington, DC, p. 343–352.
-
15)
-
M.S. Abadir ,
J.K. Reghbati
.
Functional testing of semiconductor random access memories.
ACM Comput. Surv.
,
3 ,
175 -
198
-
16)
-
R. Nair
.
Comments on an optimal algorithm for testing stuck-at faults in randomaccess memories.
IEEE Trans. Comp. (USA)
,
3 ,
258 -
261
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