A low-noise, low-power embedded modular SRAM is described. A 512 × 15 configuration at 3.3 V generates a maximum of 8.2 mA/ns dI/dt and consumes 0.24 mW/MHz, the lowest power dissipation ever reported for a modular embedded memory. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-noise low-power decoding techniques. Alternatives in the core cell, sense amplifier and read/write architecture designs are discussed. Circuit details, as well as experimental and simulation results, are presented.
References
-
-
1)
-
A.L. Silburt ,
R.S. Phillips ,
G.F.R. Gibson ,
S.W. Wood ,
A.G. Bluschke ,
J.S. Fujimoto ,
S.P. Kornachuk ,
B. Nadeau-Dostie ,
R.K. Verma ,
P.M.J. Diedrich
.
A 180-MHz 0.8-µm BiCMOS modular memory family of DRAM and multiportSRAM.
IEEE J. Solid-State Circuits
,
3 ,
222 -
232
-
2)
-
M. Aoki ,
S. Ikenaga ,
Y. Nakagome ,
M. Horiguchi ,
Y. Kawase ,
Y. Kawamoto ,
K. Itoh
.
New DRAM noise generation under half-Vcc precharge and its reductionusing a transposed amplifier.
IEEE J. Solid-State Circuits
,
4 ,
889 -
894
-
3)
-
A.R. Chandrakasan ,
S. Sheng ,
R.W. Brodersen
.
Low-power CMOS digital design.
IEEE J. Solid-State Circuits
,
4 ,
473 -
484
-
4)
-
M. Kuriyama ,
S. Atsumi ,
K. Imamiya ,
Y. Iyama ,
N. Matsukawa ,
H. Araki ,
K. Narita ,
K. Masuda ,
S. Tanaka
.
A 16-ns 1-Mb CMOS EPROM.
IEEE J. Solid-State Circuits
,
5 ,
1141 -
1146
-
5)
-
Partovi, H., Ngai, J., McGee, W.A.: `Noise suppression techniques for logic and memory circuits', Symposium on VLSI circuits digest of technical papers, 1991, p. 51–52.
-
6)
-
Hadaway, R., Kempf, P., Schvan, P., Rowlandson, M., Ho, V., Kolk, J., Tait, B., Sutherland, D., Jolly, G., Emesh, I.: `A sub-micron BiCMOS technology for telecommunications', Proceedings of European conference on Solid-state deviceresearch, 1991, p. 513–516.
-
7)
-
Desuche, J., Beyron, B., Briet, M., Ferme, P.-H.: `2μ double level metal CMOS gate array with flexible memory', Proceedings of IEEE conference on Custom integrated circuits, 1985, p. 244–247.
-
8)
-
Olmstead, J.A., Vulih, S.: `Noise problems in mixed analog-digital integrated circuits', Proceedings of IEEE conference on Custom integrated circuits, 1987, p. 659–662.
-
9)
-
Ko, U., Schenck, S., Svejda, F., La, S.: `A 0.65µm 3.3-V CMOS gate array', Proceedings of IEEE conference on Custom integrated circuits, 1992, p. 27.5.1–4.
-
10)
-
Schultz, K.J., Gibbins, R.G., Fujimoto, J.S., Phillips, R.S., Gibson, G.F.R., Silburt, A.L.: `Low-supply-noise low-power embedded modular SRAM for mixed analog-digitalICs', Proceedings of IEEE conference on Custom integrated circuits, 1992, p. 7.1.1–7.1.4.
-
11)
-
M. Ukita ,
S. Murakami ,
T. Yamagata ,
H. Kuriyama ,
Y. Nashimura ,
K. Anami
.
A single-bit-line cross-point cell activation (SCPA) architecture forultra-low-power SRAMs.
IEEE J. Solid-State Circuits
,
11 ,
1114 -
1118
-
12)
-
Chan, T., Yuen, A., Knorpp, K., Hung, M., Tsao, P., Freie, M., Chang, Y., Rasmussen, R., Hui, A., Yin, P.: `Advanced structured arrays combine high density memories with channel-freelogic array', Proceedings of IEEE conference on Custom integrated circuits, 1987, p. 39–43.
-
13)
-
Maruyama, T., Kawamura, Y., Kitagawa, N., Shinada, K., Hanada, N., Suzuki, Y.: `Wide operating voltage range and low power consumption EPROM structurefor consumer oriented ASIC applications', Proceedings of IEEE conference on Custom integrated circuits, 1988, p. 4.1.1–4.
-
14)
-
F. Miyaji ,
Y. Matsuyama ,
Y. Kanaishi ,
K. Senoh ,
T. Emori ,
Y. Hagiwara
.
A 25-ns 4-MBit CMOS SRAM with dynamic bit-line loads.
IEEE J. Solid-State Circuits
,
5 ,
1213 -
1218
-
15)
-
Shinohara, H., Matsumoto, N., Fujimori, K., Kato, S.: `A flexible multi-port RAM compiler for datapath', Proceedings of IEEE conference on Custom integrated circuits, 1990, p. 16.5.1–16.5.4.
-
16)
-
Le, T.P., Phuong, H.V., Lin, P.: `1K×128 high-performance, low-power configurable CMOS SRAM compiler', Proceedings of IEEE ASIC seminar, 1990, p. P3-5.1-4.
-
17)
-
Kimura, M., Masuda, S., Ohki, M., Yamashita, Y., Okada, K., Horiba, Y.: `A 3V, 100MHz, 35mW, dynamic line memory macro cell for HDTV applications', Proceedings of IEEE conference on Custom integrated circuits, 1992, p. 7.4.1–4.
-
18)
-
Swartz, W.P., Giuffre, C.R., Banzhaf, W.H., de Wit, M., Khan, H., McIntosh, C., Pavey, T., Thomas, D.A.: `CMOS RAM, ROM and PLA generators for ASIC applications', Proceedings of IEEE conference on Custom integrated circuits, 1986, p. 334–338.
-
19)
-
Yoshimoto, M., Anami, K., Shinohara, H., Yoshihara, T., Takagi, H., Nagao, S., Kayano, S., Nakano, T.: `A 64Kb full CMOS RAM with divided word-line structure', ISSCC digest of technical papers, 1983, p. 58–59.
-
20)
-
Ganousis, D., Collins, G., Sritharan, S., Cooper, D.: `A configurable CMOS SRAM using a seeded, laser recrystallized polysiliconon insulator process', Proceedings of IEEE conference on Custom integrated circuits, 1986, p. 55–58.
-
21)
-
Tanaka, T., Shimizu, H., Takaishi, I., Funakoshi, Y., Khono, Y., Kashimoto, Y.: `Ultra low power 16K CMOS RAM', Symposium on VLSI technology digest of technical papers, 1983, p. 38–39.
-
22)
-
H. Okuyama ,
T. Nakano ,
S. Nishida ,
E. Aono ,
H. Satoh ,
S. Arita
.
A 7.5 ns 32K×8 CMOS SRAM.
IEEE J. Solid-State Circuits
,
5 ,
1054 -
1059
-
23)
-
Sekiyama, A., Seki, T., Nagai, S., Iwase, A., Suzuki, N., Hayasaka, M.: `A 1 V operating 256-Kbit full CMOS SRAM', Symposium on VLSI circuits digest of technical papers, 1990, p. 53–54.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cds_19960014
Related content
content/journals/10.1049/ip-cds_19960014
pub_keyword,iet_inspecKeyword,pub_concept
6
6