Low-supply-noise low-power embedded modular SRAM

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Low-supply-noise low-power embedded modular SRAM

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A low-noise, low-power embedded modular SRAM is described. A 512 × 15 configuration at 3.3 V generates a maximum of 8.2 mA/ns dI/dt and consumes 0.24 mW/MHz, the lowest power dissipation ever reported for a modular embedded memory. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-noise low-power decoding techniques. Alternatives in the core cell, sense amplifier and read/write architecture designs are discussed. Circuit details, as well as experimental and simulation results, are presented.

Inspec keywords: SRAM chips; mixed analogue-digital integrated circuits

Other keywords: embedded modular SRAM; power dissipation; low-power; 3.3 V; modular embedded memory; low-noise

Subjects: Semiconductor storage; Mixed analogue-digital circuits; Memory circuits

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