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Issues in the design of a logic simulator: element modelling for efficiency

Issues in the design of a logic simulator: element modelling for efficiency

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A unique method of using inertial cancellation in the detection of set-up and hold-time violations in flip-flops and other memory-like elements is described, together with an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques.

Inspec keywords: integrated memory circuits; digital simulation; fault diagnosis; flip-flops; logic design

Other keywords: logic simulator; timing violations; hold-time violations; queues; element modelling; efficiency; inertial cancellation; memory-like elements; flip-flops; test circuit

Subjects: Memory circuits; Logic circuits; Semiconductor storage; Logic design methods

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