http://iet.metastore.ingenta.com
1887

Issues in the design of a logic simulator: element modelling for efficiency

Issues in the design of a logic simulator: element modelling for efficiency

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings - Circuits, Devices and Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A unique method of using inertial cancellation in the detection of set-up and hold-time violations in flip-flops and other memory-like elements is described, together with an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques.

References

    1. 1)
      • Kjelkerud, E., Thessen, O.: `Methods of modelling devices for logic simulation', Proceedings of 16th ACM/IEEE Design Automation Conference, 1979, p. 235–241.
    2. 2)
      • Hirschon, S.S., Hommel, M.B., Bures, C.: `Functional simulation in FANSIM3 – algorithms, data structures andresults', Proceedings of 18th ACM/IEEE Design Automation Conference, 1981, p. 248–255.
    3. 3)
      • Breuer, M.A., Parker, A.C.: `Digital system simulation; current status and future trends', Proceedings of 18th ACM/IEEE Design Automation Conference, 1981, p. 269–275.
    4. 4)
      • Hirikawa, K., Shiraki, N., Muraoka, M.: `Logic simulation for LSI', Proceedings of 19th ACM/IEEE Design Automation Conference, 1982, p. 755–762.
    5. 5)
      • Ulrich, E., Herbet, D.: `Speed and accuracy in digital network simulation based on structuralmodelling', Proceedings of 19th ACM/IEEE Design Automation Conference, 1982, p. 587–593.
    6. 6)
      • System HILO-4 HISIM reference manual. (GenRad Ltd., Maidenhead,Berks, UK, 1991).
    7. 7)
      • Krodel, T.H., Antreich, K.J.: `An accurate model for ambiguity delay simulation', Proceedings of IEEE European Design Automation Conference, 1990, p. 563–567.
    8. 8)
      • Ulrich, E.: `Table look up techniques for fast and flexible digital logic simulation', Proceedings of 17th ACM/IEEE Design Automation Conference, 1980, p. 560–563.
    9. 9)
      • A.D. Brown , M. Zwolinski , K.G. Nichols , T.J. Kazmierski . Confidence in mixed-mode simulation. Computer-Aided Design , 2 , 115 - 118
    10. 10)
      • Sherwood, W.: `A MOS modelling technique for 4-state true-value hierarchical logic simulation', Proceedings of 18th ACM/IEEE Design Automation Conference, 1981, p. 775–785.
    11. 11)
      • J.B. Gosling . (1993) Simulation in the design of digital electronic systems.
    12. 12)
      • A.D. Brown , K.G. Nichols , M. Zwolinski . Issues in the design of a logic simulator: an improved caching techniquefor event queue management. IEE Proc.-Circuits, Devices Syst. , 5 , 293 - 298
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cds_19960013
Loading

Related content

content/journals/10.1049/ip-cds_19960013
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address