A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.