access icon free Gate driver IC for enhancement mode GaN power transistors with senseFET reverse conduction detection circuit

Dead-times are necessary in switching output stage to avoid shoot-through current between the high side (HS) and the low side (LS) power transistors. However, excessively long dead-times can lead to unwanted reverse conduction and power loss. Sensing the duration of reverse conductions are especially difficult for high-voltage enhancement mode (e-mode) gallium nitride (GaN) HEMTs due to their fast switching speed. High-precision sensing circuits are required for dead-time correction as the load current changes and to withstand large voltage swings. Traditional CMOS-based sensing circuits (e.g. standard logic gates) are not suitable for GaN-based converters as they can only handle limited voltage ranges. In addition, severe undershoots (up to −4 V) may damage the sensing circuit. Here, a gate driver IC for e-mode GaN power output stages capable of detecting the presence of reverse conduction with a best resolution of 0.66 ns, a dead-time adjustment resolution of 0.33 ns, and with on-chip closed-loop control is presented. In addition, a novel reverse conduction sensing circuit that can accommodate the large voltage swings at the switching node (SW) is also described.

Inspec keywords: driver circuits; gallium compounds; III-V semiconductors; CMOS integrated circuits; power transistors; wide band gap semiconductors; power HEMT

Other keywords: dead-time correction; CMOS-based sensing circuits; reverse conduction sensing circuit; high-precision sensing circuit; gate driver IC; senseFET reverse conduction detection circuit; gallium nitride HEMT; logic gates; GaN-based converters; dead-time adjustment resolution; GaN

Subjects: CMOS integrated circuits; Other field effect devices; Power electronics, supply and supervisory circuits; Power semiconductor devices

References

    1. 1)
      • 13. Williford, P., Jones, E.A., Yang, Z., et al: ‘Optimal dead-time setting and loss analysis for GaN-based voltage source converter’. 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, USA, 2018, pp. 898905.
    2. 2)
      • 15. Song, M.K., Chen, L., Sankman, J., et al: ‘16.7 a 20 V 8.4 W 20 MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4 ns constant propagation delay and 1 ns switching rise time’. 2015 IEEE Int. Solid-State Circuits Conf. – (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015, pp. 13.
    3. 3)
      • 19. Grezaud, R., Ayel, F., Rouger, N., et al: ‘A gate driver with integrated deadtime controller’, IEEE Trans. Power Electron., 2016, 31, (12), pp. 84098421.
    4. 4)
      • 9. Dalton, J.J.O., Dymond, H.C.P., Wang, J., et al: ‘Stretching in time of GaN active gate driving profiles to adapt to changing load current’. 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, USA, 2018, pp. 34973502.
    5. 5)
      • 1. Lidow, A.: ‘Gan transistors for efficient power conversion’ (John Wiley & Sons Ltd, Chichester, UK, 2014, 2nd edn.).
    6. 6)
      • 16. Nune, R., Anurag, A., Anand, S., et al: ‘Comparative analysis of power density in Si MOSFET and GaN HEMT based flyback converters’. 2016 10th Int. Conf. on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG), Bydgoszcz, Poland, 2016, pp. 347352.
    7. 7)
      • 12. Manohar, S.K., Balsara, P.T.: ‘94.6% peak efficiency DCM buck converter with fast adaptive dead-time control’. 2013 Proc. of the ESSCIRC (ESSCIRC), Bucharest, Romania, 2013, pp. 153156.
    8. 8)
      • 17. Manohar, S.K., Balsara, P.T.: ‘High efficiency DCM buck converter with dynamic logic based adaptive switch-time control’, Analog Integr. Circuits Signal Process., 2015, 84, (3), pp. 455469.
    9. 9)
      • 22. Rangari, A.V., Gaidhani, Y.A.: ‘Design of comparator using domino logic and CMOS logic’. 2016 Online Int. Conf. on Green Engineering and Technologies (IC-GET), 2016, pp. 16.
    10. 10)
      • 10. Zhang, H., Balog, R.S.: ‘Loss analysis during dead time and thermal study of gallium nitride devices’. 2015 IEEE Applied Power Electronics Conf. and Exposition (APEC), Charlotte, NC, USA, 2015, pp. 737744.
    11. 11)
      • 8. Chen, Z., Wong, Y.T., Yim, T.S., et al: ‘A 12A 50 V half-bridge gate driver for enhancement-mode GaN HEMTs with digital dead-time correction’. 2015 IEEE Int. Symp. on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 17501753.
    12. 12)
      • 4. Ishibashi, T., Okamoto, M., Hiraki, E., et al: ‘Experimental validation of normally-on GaN HEMT and its gate drive circuit’, IEEE Trans. Ind. Appl., 2015, 51, (3), pp. 24152422.
    13. 13)
      • 7. Yan, R., Tang, S., Xi, J., et al: ‘A GaN HEMTs half-bridge driver with bandgap reference comparator clamping for high-frequency DC-DC converter’. IECON 2017 – 43rd Annual Conf. of the IEEE Industrial Electronics Society, Beijing, People's Republic of China, 2017, pp. 539545.
    14. 14)
      • 21. Niwa, A., Imazawa, T., Kojima, R., et al: ‘A dead-time-controlled gate driver using current-sense FET integrated in SiC MOSFET’, IEEE Trans. Power Electron., 2018, 33, (4), pp. 32583267.
    15. 15)
      • 18. Zhao, A., Fomani, A.A., Ng, W.T.: ‘One-step digital dead-time correction for DC-DC converters’. 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conf. and Exposition (APEC), Palm Springs, CA, USA, 2010, pp. 132137.
    16. 16)
      • 11. Grezaud, R., Ayel, F., Rouger, N., et al: ‘A gate driver with integrated deadtime controller’, IEEE Trans. Power Electron., 2016, 31, (12), pp. 84098421.
    17. 17)
      • 2. Kinzer, D.: ‘Gan power IC technology: past, present, and future’. 2017 29th Int. Symp. on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017, pp. 1924.
    18. 18)
      • 6. Wang, B., Tipirneni, N., Riva, M., et al: ‘An efficient high-frequency drive circuit for GaN power HFETs’, IEEE Trans. Ind. Appl., 2009, 45, (2), pp. 843853.
    19. 19)
      • 5. Yu, J., Zhang, W.J., Shorten, A., et al: ‘A smart gate driver IC for GaN power transistors’. 2018 IEEE 30th Int. Symp. on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, USA, 2018, pp. 8487.
    20. 20)
      • 20. Schirone, L., Macellari, M., Pellitteri, F.: ‘Predictive dead time controller for GaN-based boost converters’, IET Power Electron., 2017, 10, (4), pp. 421428.
    21. 21)
      • 23. Priyanka, C., Latha, P.: ‘Design and implementation of time to digital converters’. 2015 Int. Conf. on Innovations in Information, Embedded and Communication Systems (ICIIECS), Coimbatore, India, 2015, pp. 14.
    22. 22)
      • 14. Zhang, W.J., Leng, Y., Yu, J., et al: ‘A gate driver IC for enhancement mode GaN power GaN transistors with precise dead-time correction’. IEEE 14th Int. Seminar on Power Semiconductors (ISPS), Prague, Czech Republic, 2018.
    23. 23)
      • 3. Rose, M., Wen, Y., Fernandes, R., et al: ‘A GaN HEMT driver IC with programmable slew rate and monolithic negative gate-drive supply and digital current-mode control’. 2015 IEEE 27th Int. Symp. on Power Semiconductor Devices & IC's (ISPSD), Hong Kong, People's Republic of China, 2015, pp. 361364.
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