access icon free Design of high-speed gate driver to reduce switching loss and mitigate parasitic effects for SiC MOSFET

© The Institution of Engineering and Technology
Received 16/12/2016, Accepted 25/04/2017, Revised 28/03/2017, Published 26/04/2017

The high switching speed in a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) will aggravate the parasitic effects (di/dt and dv/dt) arising from the interaction with parasitic elements. In this project, a high-speed gate driver has been developed and optimised for the commercially available SiC MOSFET power module. The impact of various parasitic parameters on parasitic effects is initially evaluated. Then, an improved gate-assisted circuit is proposed with a local low-impedance path for both discharging and Cdv/dt currents. It allows maximised turn-off speed (dv/dt up to 36 V/ns) and minimised turn-off loss (reduction up to 70%). It also produces a reduction in electromagnetic interference. The gate voltage spike due to Cdv/dt current is reduced below the threshold voltage at various testing conditions.

Inspec keywords: MOSFET; interference suppression; driver circuits; wide band gap semiconductors; silicon compounds

Other keywords: parasitic effect mitigation; gate voltage spike reduction; discharging currents; threshold voltage; local low-impedance path; parasitic parameters; electromagnetic interference reduction; metal-oxide-semiconductor field-effect transistor; improved gate-assisted circuit; SiC; minimised turn-off loss; silicon carbide MOSFET power module; switching loss reduction; maximised turn-off speed; high-speed gate driver design

Subjects: Power electronics, supply and supervisory circuits; Insulated gate field effect transistors; Electromagnetic compatibility and interference

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