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Simulation study of single event effects for split-gate enhanced power U-shape metal-oxide semiconductor field-effect transistor

Simulation study of single event effects for split-gate enhanced power U-shape metal-oxide semiconductor field-effect transistor

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Power metal-oxide semiconductor field-effect transistors (MOSFETs) are increasingly used in the space probes where the environment is composed of various kinds of particles. Thus, it is essential to study the influence of the natural radiation environment on the electrical behaviour of MOSFETs in space. This study presents two-dimensional numerical simulation results, which investigates the sensitive volume, triggering criteria and characteristics of single-event burnout (SEB) and single-event gate rupture (SEGR) for the split-gate enhanced power U-shape MOSFET (SGE-UMOS). In addition, the comparison of the standard Trench-UMOS and SGE-UMOS for both SEB and SEGR simulation results is investigated. The SGE-UMOS shows an improved SEB performance than the standard Trench-UMOS with a larger safe operating area. The SGE-UMOS can also contribute to protect against SEGR compared with standard Trench-UMOS.

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    15. 15)
    16. 16)
    17. 17)
      • 17. Wang, Y., Hu, H.F., Jiao, W.L., Cheng, C.: ‘High-performance gate-enhanced power UMOSFET with optimized structure’, IEEE Electron Device Lett., 2010, 31, (11), pp. 12811283.
    18. 18)
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