© The Institution of Engineering and Technology
Design and implementation of a fully table look-up digital pulse-width modulation (DPWM) controller for high-frequency DC–DC buck conversion is presented. The controller comprises a 1 bit analogue comparator, a digital error process unit and a fully table look-up multi-phase DPWM. The interface of analogue-to-digital conversion is performed with the analogue comparator. Moreover, the proposed programmable memory is based on the table look-up multi-phase approach for the functions of the proportional-integral-derivative (PID) compensation, which alleviates the penalty of using large chip-area multipliers. As a result, the approach is very suitable for system-on-a-chip (SOC) implementation. A prototype test chip is realised to validate the mechanism of the proposed architecture.
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