access icon free Design and analysis of wideband low-power LNA for improved RF performance with compact chip area

Here, a wideband low-noise amplifier (LNA) based on the two-stage cascade configuration is presented to improve the radiofrequency (RF) performance. With the common gate (CG) input stage, the proposed LNA provides wideband input matching, while the wideband gain response was achieved using the peaking inductors inserted at the drain terminals of each stage. With a standard CMOS process, the chip area of the proposed wideband LNA is only 0.116 mm2. However, it consumes a 5.4 mW power from a supply voltage of . From the post-layout simulation results, it achieves maximum power gain of 11.13 dB at 8.5 GHz, input return loss below −9.44 dB, reverse isolation less than −60 dB, and small group delay variation of ±97 ps across 8.5–20 GHz frequency range. Moreover, noise figure (NF) lies in the range of 2.19–3.23 dB, whereas the NF minimum () varies in the range of 1.55–2.91 dB for 8.5–20 GHz frequency range. Apart from this, the proposed LNA achieves an IIP3 of 0.96 dBm, when a two-tone test is performed with a frequency spacing of 50 MHz.

Inspec keywords: field effect MMIC; low noise amplifiers; CMOS analogue integrated circuits; low-power electronics; integrated circuit design; wideband amplifiers; MMIC amplifiers

Other keywords: wideband low-power LNA analysis; wideband gain response; noise figure; improved RF performance; CMOS process; input return loss; radiofrequency performance; small group delay variation; common gate input stage; wideband input matching; peaking inductors; wideband low-power LNA design; power 5.4 mW; drain terminals; voltage 1 V; two-stage cascade configuration; size 0.18 mum; reverse isolation loss; wideband low-noise amplifier; post-layout simulation; frequency 8.5 GHz to 20 GHz; noise figure 2.19 dB to 3.23 dB

Subjects: CMOS integrated circuits; Amplifiers; Analogue circuit design, modelling and testing; Microwave integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing

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