This work presents a novel approach to computationally efficient Pareto front identification for variable-turn on-chip inductors. The final outcome is a set of solutions that correspond to the best trade-offs between conflicting design objectives. Here, we consider minimising inductor area and, simultaneously, maximising its quality factor, while maintaining a specified inductance value at a given operating frequency. As opposed to the typically used population-based metaheuristics requiring massive computational resources to generate the entire Pareto front in a single algorithm run, the proposed method reduces the number of necessary structure evaluations by exploiting a point-by-point strategy for determining the consecutive trade-off designs. The original design problem is a mixed-integer task involving integer and non-integer variables (here, the number of inductor windings and its geometry parameters). For the sake of computational efficiency, we develop a separate kriging interpolation model for each considered case of winding turns, and use it, instead of expensive electromagnetic simulations, to obtain the initial Pareto fronts. The non-dominated part of the concatenated initial Pareto sets is subsequently elevated (accuracy-wise) to the level of an electromagnetic analysis by means of a response correction technique. Our considerations are illustrated using a 3.5-nH variable-turn on-chip inductor realised in 65-nm CMOS technology.

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Expedited EM-driven generation of Pareto-optimal trade-off curves for variable-turn on-chip inductors

References

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