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access icon free Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM

© The Institution of Engineering and Technology
Received 25/08/2016, Accepted 12/02/2017, Revised 17/01/2017, Published 15/02/2017

This study presents a multi-level 2D discrete wavelet transform (DWT) architecture without off-chip RAM. Existing architectures use one off-chip RAM to store the image data, which increases the complexity of the system. For one-chip design, line-based architecture based on modified lifting scheme is proposed. By replacing the multipliers with canonic sign digit multipliers, a critical path of one full-adder delay is achieved. As per theoretical estimate, for three-level 2D DWT with an image of N × N size, the proposed architecture requires 123 adders, 66 subtracters, 167 registers, temporal memory of 7.5N words and input RAM of 3N bytes. The estimated hardware requirement shows that for the image size of 512 × 512 and three-level DWT, the proposed architecture involves at least 14.1% less transistor-delay-product than existing architectures.

Inspec keywords: integrated circuit design; discrete wavelet transforms; random-access storage

Other keywords: full-adder delay; transistor delay product; image data; off-chip ram; hardware efficient multiplier less multilevel 2D DWT architecture; hardware requirement; canonic sign digit multipliers; one-chip design; line based architecture; lifting scheme; temporal memory

Subjects: Semiconductor storage; Integral transforms; Memory circuits; Digital circuit design, modelling and testing; Integral transforms

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