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access icon free Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory

  • Author(s): Shizhong Li 1, 2 ; Haibing Yin 3 ; Xiangzhong Fang 2 ; Huijuan Lu 1
    • View affiliations
    • Affiliations: 1: School of Information Engineering, China Jiliang University, Hangzhou, People's Republic of China ;
      2: School of Electronic Information and Electrical Engineering, Shang Jiaotong University, Shanghai, People's Republic of China ;
      3: School of Communication Engineering, Hangzhou Dianzi University, Hangzhou, People's Republic of China
  • Source: Volume 11, Issue 6, June 2017, p. 379 – 388
    DOI:  10.1049/iet-ipr.2016.0636 , Print ISSN 1751-9659, Online ISSN 1751-9667
© The Institution of Engineering and Technology
Received 05/08/2016, Accepted 23/02/2017, Revised 18/01/2017, Published 24/02/2017

In high definition (HD) video coders, huge memory access bandwidth is the major throughput bottleneck. Lossless embedded compression is an efficient solution to alleviate the bandwidth burden, in which image are compressed before writing into local memory and decompressed after retrieving from local memory. This study proposes a hardware-oriented lossless image compression algorithm, supporting block and line random access flexibly for adapting diverse hardware video codec architectures. The major contributions are characterised as follows. First, block or pixel-level adaptive prediction is proposed to fully utilise the image spatial correlation by employing adaptive mode decision. Second, multiple-range semi-fixed (SF) variable length coding (VLC) is employed to describe the prediction residue, and adaptive block size selection is employed for SF VLC to fully utilise the statistical redundancy. In addition, Huffman VLC is further employed to represent the control syntax elements. Third, four-stage pipeline hardware architecture is proposed to implement the proposed algorithm. Simulation results show that the proposed algorithm achieves competitive rate compression performance compared with reference algorithms. The proposed hardware architecture is verified supporting real-time processing for quad-HD videos at the frequency of 166 MHz. The proposed work achieves reducing memory access bandwidth by ∼55.2%, which is useful for hardwired video coding.

Inspec keywords: statistical analysis; CMOS integrated circuits; prediction theory; high definition video; video coding; variable length codes; Huffman codes; data compression

Other keywords: four-stage pipeline hardware architecture; SDRAM; multiple-range SF VLC; image spatial correlation; control overheads; hardware-oriented lossless image compression algorithm; external memory; synchronous dynamic random access memory; competitive rate compression performance; pixel-level adaptive intraprediction; memory access bandwidth; frequency 166 MHz; adaptive block size selection; real-time processing; prediction residue; image pixels; mode decision; block random access patterns; reference algorithms; syntax elements; bandwidth reduction; hardwired high definition video coder; quad-HD videos; statistical redundancy; system throughput bottleneck; block prediction modes; complementary metal-oxide-semiconductor technology; pixel prediction modes; reference image; lossless embedded compression; Huffman VLC; size 90 nm; TSMC; multiple-range semifixed variable length coding; line random access patterns

Subjects: Other topics in statistics; Image and video coding; Other topics in statistics; Video signal processing; High definition television and video

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