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Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory

Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory

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In high definition (HD) video coders, huge memory access bandwidth is the major throughput bottleneck. Lossless embedded compression is an efficient solution to alleviate the bandwidth burden, in which image are compressed before writing into local memory and decompressed after retrieving from local memory. This study proposes a hardware-oriented lossless image compression algorithm, supporting block and line random access flexibly for adapting diverse hardware video codec architectures. The major contributions are characterised as follows. First, block or pixel-level adaptive prediction is proposed to fully utilise the image spatial correlation by employing adaptive mode decision. Second, multiple-range semi-fixed (SF) variable length coding (VLC) is employed to describe the prediction residue, and adaptive block size selection is employed for SF VLC to fully utilise the statistical redundancy. In addition, Huffman VLC is further employed to represent the control syntax elements. Third, four-stage pipeline hardware architecture is proposed to implement the proposed algorithm. Simulation results show that the proposed algorithm achieves competitive rate compression performance compared with reference algorithms. The proposed hardware architecture is verified supporting real-time processing for quad-HD videos at the frequency of 166 MHz. The proposed work achieves reducing memory access bandwidth by ∼55.2%, which is useful for hardwired video coding.

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