http://iet.metastore.ingenta.com
1887

Security and fault tolerance evaluation of TMR–QDI circuits

Security and fault tolerance evaluation of TMR–QDI circuits

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Information Security — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors report the results of a study on the impact of resistive bridging faults on triple modular redundancy (TMR)-based quasi-delay-insensitive (QDI) asynchronous countermeasures, which is used to provide a secure circuit against power analyses. They have carried out the present study on CADENCE using a resistive bridges fault model. They show that the resistive bridge faults can have serious impacts on the security of integrated circuits and it is possible to discover the secret data. Based on the bridges resistance value, there are three operating intervals of secure circuits, in which TMR-based QDI may or may not function correctly in the presence of two resistive bridge faults depending on the interval of the resistance value.

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-ifs.2018.5439
Loading

Related content

content/journals/10.1049/iet-ifs.2018.5439
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address