Sampling and controlling faster than the computational delay

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Sampling and controlling faster than the computational delay

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Published

For a sampled-data control system, the authors propose to choose the time between samples to be shorter than the computational delay involved in computing the control signal, an approach called as intra-delay sampling. It is shown that, utilising a parallel computing architecture, this is indeed feasible and that intra-delay sampling schemes yield better performance than their slower sampling counterparts.

Inspec keywords: sampled data systems; delays; parallel architectures; sampling methods

Other keywords: parallel computing architecture; control signal; intra-delay sampling schemes; computational delay; sampled-data control system

Subjects: Distributed parameter control systems; Discrete control systems; Parallel architecture; Other topics in statistics

References

    1. 1)
      • K.J. Astrom , B. Wittenmark . (1997) Computer-controlled systems: theory and design.
    2. 2)
      • Xilinx: Xilinx, Inc., Virtex FPGA family, http://www.xilinx.com/products/devices.htm, 2010.
    3. 3)
      • Buchstaller, D.: `Robust stability and performance for multiple model switched adaptive control', 2010, PhD, University of Southampton, School of Electronics and Computer Science (ECS).
    4. 4)
      • Lopes, A.R., Constantinides, G.A.: `A fused hybrid floating-point and fixed-point dot-product for FPGAs', Proc. Int. Symp. Applied Reconfigurable Computing, 2010, Bangkok, Thailand, p. 157–168.
    5. 5)
      • D.A. Patterson , J.L. Hennessy . (2007) Computer architecture: a quantitative approach.
    6. 6)
      • Xilinx: Xilinx, Inc., Core generator, version 9.0.2, http://www.xilinx.com, 2010.
    7. 7)
    8. 8)
    9. 9)
      • Asanovic, K., Bodik, R., Catanzaro, B.C.: `The landscape of parallel computing research: a view from Berkeley', Technical Report UCB/EECS-2006-183, 2006.
    10. 10)
      • (2009) Semiconductor Industry Association (SIA).
    11. 11)
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