Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes

Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes

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The authors propose the construction of spatially coupled low-density parity-check (SC-LDPC) codes using a periodic time-variant quasi-cyclic (QC) algorithm. The QC-based approach is optimised to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for a Xilinx field-programmable gate array (FPGA), to compare the logic and memory requirements for various approaches. It is shown that the proposed QC SC-LDPC code (with optimisation) can be stored with reasonable logic resources and without the need of block memory in the FPGA. In addition, a significant improvement in the processing speed is also achieved. This study also proposes a new QC algorithm for constructing spatially coupled repeat-accumulate (SC-RA) codes. The proposed construction reduces the implementation complexity of the encoder and subsequently saves significant computational resources required for storing and accessing the circulants in the decoder. The performance of the proposed code is also compared with the standard RA codes through simulations.


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