http://iet.metastore.ingenta.com
1887

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Communications — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Novel high-throughput architecture for a turbo decoder, which has been conceived by combining the advantages of pipelining and parallel processing, is proposed. Increase in throughput has been achieved by pipelining the add compare select offset (ACSO) unit and advancing the normalisation process in the ACSO unit based on global overflow protection logic. The proposed turbo decoder also benefits from incorporating low-complexity contention-free interleaver. The present work has demonstrated that a 32 maximum a posteriori probability (MAP) decoder core achieves a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm process technology. Thus, the proposed turbo decoder meets the throughput requirement of modern wireless communication standards like third-generation partnership project (3GPP) long-term evolution (LTE).

References

    1. 1)
      • Berrou, C., Glavieux, A., Thitimajshima, P.: `Near Shannon limit error correcting coding and decoding: turbo-codes', Proc. IEEE Int. Conf. on Communications, May 1993, p. 1064–1070.
    2. 2)
      • Recommendation for Space Data System Standards: ‘TM Synchronization and Channel Coding’, 2003.
    3. 3)
      • Third Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and Channel Coding (Release 9) 3GPP Organizational Partners TS 36.212, Rev. 8.3.0, May 2008.
    4. 4)
      • CDMA2000 High Rate Packet Data Air Interface Specification 3GPP2 C.S0024-B Version 1.0, May 2006.
    5. 5)
      • (2004) Air interface for fixed broadband wireless access systems.
    6. 6)
      • ETSI EN 302-583 V1.1.1: ‘Digital Video Broadcasting (DVB), Framing Structure, Channel Coding and Modulation for Satellite Services to Handheld Devices (SH) below 3 GHz’, March 2008.
    7. 7)
      • Hagenauer, J., Hoeher, P.: `A Viterbi algorithm with soft-decision outputs and its applications', Proc. IEEE Globecom, 1989, p. 1680–1686.
    8. 8)
    9. 9)
    10. 10)
    11. 11)
      • Robertson, P., Villebrun, E., Hoeher, P.: `A comparison of optimal and sub optimal MAP decoding algorithms operating in the log domain', Proc. IEEE Int. Conf. Communications, 1995, p. 1009–1013.
    12. 12)
      • C.M. Wu , M.D. Shieh , C.H. Wu , Y.T. Hwang , J.H. Chen . VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. VLSI Syst. , 2 , 439 - 447
    13. 13)
      • Worm, A., Lamm, H., Wehn, N.: `VLSI architectures for high-speed MAP decoders', Proc. 14th Int. Conf. VLSI Design, 2001, p. 446–453.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
      • Prescher, G., Gemmeke, T., Noll, T.G.: `A parametrizable low-power high-throughput turbo-decoder', IEEE Int. Conf. Acoustics, Speech, and Signal Processing (ICASSP), March 2005, p. 25–28, vol. 5.
    18. 18)
    19. 19)
    20. 20)
      • Urard, P., Paumier, L., Viollet, M.: `A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder', IEEE Int. Solid-State Circuit Conf., February 2004, p. 424–536.
    21. 21)
      • Studer, C., Benkeser, C., Belfanti, S., Huang, Q.: `A 390 Mb/s 3.57 mm', Proc. IEEE ISSCC Digest, Technical Papers, February 2010, San Francisco, USA, p. 274–275.
    22. 22)
      • Bickerstaff, M., Davis, L., Thomas, C., Garrett, D., Nicol, C.: `A 24 Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless', Proc. IEEE ISSCC Digest, Technical Papers, February 2003, San Francisco, USA, p. 150–484.
    23. 23)
      • Bougard, B., Giulietti, A., Derudder, V.: `A scalable 8.7 nj/bit 75.6 Mb/s parallel concatenated convolutional (turbo-) codec', IEEE Int. Solid-State Circuit Conf., February 2003, p. 152–484.
    24. 24)
    25. 25)
    26. 26)
    27. 27)
    28. 28)
      • Singh, A., Boutillon, E., Masera, G.: `Bit-width optimization of extrinsic information in turbo decoder', Proc. Int. Symp. Turbo Codes Related Topics, 2008, p. 134–138.
    29. 29)
      • K.K. Parhi . (2003) VLSI digital signal processing systems: design and implementation.
    30. 30)
      • Thul, M.J., Gilbert, F., Wehn, N.: `Optimized concurrent interleaving architecture for high-throughput turbo-decoding', Proc. Int. Conf. Electronics Circuits and Systems, September 2002, Dubrovnik, Croatia, p. 1099–1102.
    31. 31)
    32. 32)
    33. 33)
    34. 34)
      • Nimbalker, A., Blankenship, T.K., Classon, B., Fuja, T.E., Costello, D.J.: `Inter-window shuffle interleavers for high throughput turbo decoding', Proc. Third Int. Symp. on Turbo Codes and Related Topics, September 2003, p. 355–358.
    35. 35)
    36. 36)
    37. 37)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-com.2011.0713
Loading

Related content

content/journals/10.1049/iet-com.2011.0713
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address