High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver

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Novel high-throughput architecture for a turbo decoder, which has been conceived by combining the advantages of pipelining and parallel processing, is proposed. Increase in throughput has been achieved by pipelining the add compare select offset (ACSO) unit and advancing the normalisation process in the ACSO unit based on global overflow protection logic. The proposed turbo decoder also benefits from incorporating low-complexity contention-free interleaver. The present work has demonstrated that a 32 maximum a posteriori probability (MAP) decoder core achieves a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm process technology. Thus, the proposed turbo decoder meets the throughput requirement of modern wireless communication standards like third-generation partnership project (3GPP) long-term evolution (LTE).


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