Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

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The authors propose a compact and fast fading channel simulator for the baseband verification and prototyping of multiple-input multiple-output (MIMO) wireless communication systems. The simulator accurately and efficiently implements models of both single-bounce and multiple-bounce geometric propagation conditions. Fading samples are generated at a low rate, comparable to the Doppler frequency, and then interpolated to match the desired sample rate. Bit-true simulations verify the accuracy of the hardware simulator. As an example, when implemented on a Xilinx XC5VLX110 field-programmable gate array (FPGA), the 4×4 MIMO geometric fading channel simulator occupies only 6.6% of the configurable slices while generating more than 16×324 million samples per second. The geometric MIMO fading channel simulator is well suited for use in an FPGA-based error rate performance verification system.


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