Parallel reconfigurable decoder architectures for rotation LDPC codes

Parallel reconfigurable decoder architectures for rotation LDPC codes

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Communications — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.


    1. 1)
      • Good error-correcting codes based on very sparse matrices
    2. 2)
      • Improved low-density parity-check codes using irregular graphs
    3. 3)
      • On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit
    4. 4)
      • Fundamentals of codes, graphs, and iterative decoding
    5. 5)
      • Codes and iterative decoding on general graphs
    6. 6)
      • On the implementation of min–sum algorithm and its modifications for decoding low-density parity-check codes
    7. 7)
      • Reduced-complexity decoding of LDPC codes
    8. 8)
      • Jones, C., Valles, E., Smith, M., Villasenor, J.: `Approximate-min constraint node updating for LDPC code design', IEEE Conf. Military Communication, MILCOM 2003, October 2003, p. 157–162
    9. 9)
      • Mansour, M.M., Shanbhag, N.R.: `Memory efficient turbo decoder architecture for LDPC codes', IEEE Workshop on Signal Processing Systems, ISPS'2002, October 2002, p. 159–164
    10. 10)
      • Memory-efficient sum–product decoding of LDPC codes
    11. 11)
      • Modified sum–product algorithms for decoding low-density parity-check codes
    12. 12)
      • Block-interlaced LDPC decoders with reduced interconnect complexity
    13. 13)
      • Kiran, K.G., Gwan, S.C., Mark, B.Y.: `A parallel VLSI architecture for layered decoding for array LDPC codes', 20thInt. Conf. VLSI Design, 2007, p. 738–743
    14. 14)
      • Mohsenin, T., Baas, B.M.: `High-throughput LDPC decoders using a multiple split-row method', IEEE Int. Conf. Acoustics, Speech and Signal Processing (ICASSP 2007), 2007, 2, p. 13–16
    15. 15)
      • A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes
    16. 16)
      • Echard, R., Shih-Chun, C.: `The π-rotation low-density parity check codes', IEEE Global Telecommunications Conf. (GLOBECOM'01), 2001, 2, p. 980–984
    17. 17)
      • Echard, R., Shih-Chun, C.: `Design considerations and performance analysis of good π-rotation LDPC codes', Proc. Wireless Telecommunication Symp., April 2006, p. 1–5

Related content

This is a required field
Please enter a valid email address