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Interconnect and communication synthesis for distributed register-file microarchitecture

Interconnect and communication synthesis for distributed register-file microarchitecture

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Distributed register-file microarchitecture (DRFM), which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register-based architecture, DRFM offers an opportunity of reducing the cost of global (inter-island) connections by confining as many of the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimising inter-island connections (IICs) and (problem 2) data transfer (i.e. communication) scheduling through the IICs for minimising access conflicts among data transfers. By solving problem 1, the design complexity because of the long interconnect delay is minimised, whereas by solving problem 2, the additional latency required to resolve the register-file access conflicts among the inter-island data transfers is minimised. This work proposes novel solutions to the two problems. Specifically, for problem 1, previous work solves it in two separate steps: (i) scheduling and (ii) then determining the IICs by resource binding to islands. However, in this algorithm called DFRM-int, the authors place primary importance on the cost of interconnections. Consequently, the authors minimise the cost of interconnections first to fully exploit the effects of scheduling on interconnects and then to schedule the operations later. For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in this algorithm called DFRM-com, the authors devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution. By applying this proposed synthesis approach DFRM-int+DFRM-com, the authors are able to further reduce the IICs by 17.9%, compared with that by the conventional DRFM approach, even completely eliminating register-file access conflicts without any increase of latency.

References

    1. 1)
      • Magen, N., Kolodny, A., Weiser, U., Shamir, N.: `Interconnect-power dissipation in a microprocessor', Proc. Int. Workshop on System Level Interconnect Prediction, April 2004, p. 7–13.
    2. 2)
      • Singh, A., Marek-Sadowska, M.: `Efficient circuit clustering for area and power reduction in FPGAs', Proc. Int. Symp. Field-Programmable Gate Arrays, February 2002, p. 59–66.
    3. 3)
      • Kusse, E., Rabaey, J.: `Low-energy embedded FPGA structures', Proc. Int. Symp. Low Power Electronics and Design, August 1998, p. 155–160.
    4. 4)
      • Cong, J., Fan, Y., Jiang, W.: `Platform-based resource binding using a distributed register-file microarchitecture', Proc. Int. Conf. Computer Aided Design, November 2006, p. 709–715.
    5. 5)
      • Xilinx Website, http://www.xilinx.com.
    6. 6)
      • Altera Website, http://www.altera.com.
    7. 7)
      • Tarafdar, S., Leeser, M., Yin, Z.: `Integrating floorplanning in data transfer based high-level synthesis', Proc. Int. Conf. Computer Aided Design, November 1998, p. 412–417.
    8. 8)
      • Jang, H.-J., Pangrle, B.M.: `A grid-based approach for connectivity binding with geometric costs', Proc. Int. Conf. Computer Aided Design, November 1993, p. 94–99.
    9. 9)
    10. 10)
      • Lee, H.-D., Hwang, S.-Y.: `A scheduling algorithm for multiport memory minimization in datapath synthesis', Proc. Asia South Pacific Design Automation Conf. '95, January 1995, p. 93–100.
    11. 11)
    12. 12)
      • Kim, D., Shin, D., Choi, K.: `High-level synthesis under multi-cycle interconnect delay', Proc. Asia South Pacific Design Automation Conf., January 2001, p. 662–667.
    13. 13)
      • Kim, D., Jung, J., Lee, S., Jeon, J., Choi, K.: `Behavior-to-placed RTL synthesis with performance-driven placement', Proc. Int. Conf. Computer Aided Design, November 2001, p. 320–325.
    14. 14)
    15. 15)
    16. 16)
      • Fiduccia, C., Matteyses, R.: `A Linear-time heuristic for improving network partitions', Proc. Design Automation Conf., June 1988, p. 241–247.
    17. 17)
      • R.E. Tarjan . (1983) Data structures and network algorithms.
    18. 18)
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