Autonomous temperature control technique in VLSI circuits through logic replication

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Autonomous temperature control technique in VLSI circuits through logic replication

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Published

A temperature reduction technique at the gate level that reduces the peak temperature through thermal-aware logic replication is presented. The technique identifies the hottest part of a given gate-netlist, extracts this from the netlist and replicates it in order to migrate the computation from one unit to the copied one whenever it exceeds a given maximum threshold temperature. The resulting gate netlist is then replaced using a thermal-aware floorplanner in order to maximise temperature reduction gain. To allow the migration from one unit to the other without any timing penalty, multiplexors and de-multiplexors between both units are inserted as well as a simple control unit with a thermal sensor on each replicated unit. Our technique ensures that only those parts of the circuit that have a high power density are replicated, and provides an autonomous hardware thermal-controlling mechanism that self-regulates itself and allows the context to swap to any replicated unit without any timing penalty. An entire temperature reduction framework is built on the top of this technique that incorporates a thermal simulator, thermal-aware floorplanner, power estimators as well as a graphical interface to manage these tools. Experimental results show that the proposed technique efficiently identifies the hottest parts of a gate netlist, replicates these and inserts the de-muxes and muxes, lowering the final peak temperature by up to 20.27°C. Further, it reduces the overall leakage power by up to 35.98%.

Inspec keywords: semiconductor device packaging; VLSI; circuit layout; circuit CAD; temperature control

Other keywords: gate netlist; thermal-aware logic replication; power estimators; autonomous temperature control; VLSI circuits; graphical interface; thermal-aware floorplanner

Subjects: Product packaging; Electronic engineering computing; Computer-aided circuit analysis and design; Semiconductor integrated circuit design, layout, modelling and testing; Thermal variables control

References

    1. 1)
      • S. Borkar . Design challenges of technology scaling. IEEE Micro , 4 , 509 - 519
    2. 2)
      • Boemo, S., Lopez-Buedo, S.: `Themal monitoring on FPGAs using ring–oscillators', LNCS, 1997, 1304, p. 69–78.
    3. 3)
      • Akgul, B.S., George, J., Marr, B., Palem, K.V.: `Probabilistic arithmetic and energy efficient embedded signal processing', Proc. Int. Conf. Compilers, Architectures, and Synthesis of Embedded Systems (CASES), 2006, p. 158–169.
    4. 4)
      • Skadron, K., Stan, M.R., Huang, W., Velusamy, S., Sankaranarayanan, K., Tarjan, D.: `Temperature-aware microarchitecture', Proc. Int. Symp. Computer Architecture (ISCA), 2003, p. 2–13.
    5. 5)
      • Gu, Z., Wang, J., Dick, R.P., Zhou, H.: `Incremental exploration of the combined physical and behavioral design space', Proc. Design Automation Conf. (DAC), 2005, p. 208–213.
    6. 6)
      • F. Fallah , M. Pedram . Standby and active leakage current control and minimization of CMOS VLSI circuits. IEICE Trans. Electron. , 509 - 519
    7. 7)
      • Huang, W., Stan, M.R., Skadron, K., Sankaranarayanan, K., Ghosh, S., Velusamy, S.: `Compact thermal modeling for temperature-aware design', Proc. Design Automation Conf. (DAC), 2004, p. 878–883.
    8. 8)
      • Skadron, K.: `Temperature-aware microarchitecture: extended discussion and results', Tech. Report CS-2003-08, April 2003.
    9. 9)
      • Schafer, B.C., Lee, Y., Kim, T.: `Temperature-aware compilation for VLIW processors', Proc. 13th IEEE Int. Conf. Embedded and Real-Time Computing Systems and (RTCSA), 2007.
    10. 10)
      • Mukjerjee, R., Memik, S.O., Memik, G.: `Temperature-aware resource allocation and binding in high-level synthesis', Design Automation Conf. (DAC), 2005.
    11. 11)
      • Kim, H.S., Vijaykrishnan, N., Kandemir, M., Irwin, M.J.: `Adapting instruction level parallelism for optimizing leakage in VLIW architectures', Proc. Int. Conf. Language, Compilers and Tools for Embedded Systems (LCTES), 2003, p. 275–283.
    12. 12)
      • Wong, D.F., Liu, C.L.: `A new algorithm for floorplan design', Proc. Design Automation Conf. (DAC), 1986, p. 101–107.
    13. 13)
      • Otten, R.H.J.M.: `Automatic floorplan design', Proc. Design Automation Conf. (DAC), 1982, p. 261–267.
    14. 14)
      • Lim, C.-H., Daasch, W., Cai, G.: `A thermal-aware superscalar microprocessor', Proc. Int. Symp. Quality Electronic Design (ISQED), 2002, p. 517–522.
    15. 15)
      • Tsai, C.H., Kang, S.M.: `Standard cell placement for even on-chip thermal distribution', Int. Symp. Physical Design, 1999, p. 179–185.
    16. 16)
      • Hodges , Jackson . (1982) Analysis and design of digital integrated circuits.
    17. 17)
      • Malik, S., Coudert, O., Cong, J., Sarrafzadeh, M.: `Incremental CAD', Proc. Int. Conf. Computer-Aided Design (ICCAD), 2000, p. 236–243.
    18. 18)
      • M. Pedram , S. Nazarian . Thermal modeling, analysis, and management in VLSI circuits: principles and methods. Proc. IEEE, special issue on Thermal Analysis of ULSI , 8 , 1487 - 1501
    19. 19)
      • Synopsys Design Compiler: http://www.synopsys.com.
    20. 20)
      • Y.A. Cengel . (1996) Introduction to thermodynamics and heat transfer.
    21. 21)
      • Tsai, C.H., Kang, S.M.: `Standard cell placement for even on-chip thermal distribution', Int. Symp. Physical Design, 1999.
    22. 22)
      • Ni, M., Memik, S.O.: `Thermal-induced leakage power optimization by redundant resource allocation', Proc. Int. Conf. Computer-Aided Design (ICCAD), 2006, p. 297–302.
    23. 23)
      • Han, Y., Koren, I., Moritz, C.A.: `Temperature aware floorplanning', Proc. 2nd Workshop on Temperature-Aware Computer Systems (TACS-2), 2005.
    24. 24)
      • Sabry, M.N.: `Dynamic compact thermal models: an overview of current and potential advances', Int. Workshop on Thermal Investigations of ICs and Systems, 2001.
    25. 25)
      • ‘Understanding integrated circuit package power capabilities’, http://www.national.com, accessed April 2000, pp.291–301.
    26. 26)
      • C.C. Chu , D.F. Wong . A matrix synthesis approach to thermal placement. IEEE Trans. Comput. Aided Des. , 11 , 1166 - 1174
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