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The design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the Sum of Absolute Differences algorithm, is presented. Model-based designs are followed, and a parameterisable open source VHDL library component appropriate for integration within a system-on-a-programmable chip is created. We target a field programmable gate array board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100 MHz. The hardware co-processor produces dense 8-bit disparity maps of 320×240 pixels at a rate of 25 Mpixels/s and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16 000 logic elements, whereas by migrating to more complex devices the design can easily grow to support better results.
References
-
-
1)
-
Masrani, D.K., Maclean, W.J.: `A real-time large disparity range stereo-system using FPGAs', Proc. Fourth IEEE Int. Conf. Computer Vision Systems (ICVS 2006), January 2006, New York, USA, p. 13–20.
-
2)
-
Kotoulas, L., Gasteratos, A., Sirakoulis, G., Georgoulas, Ch., Andreadis, I.: `Enhancement of fast acquired disparity maps using a 1-D cellular automaton filter', Proc. Fifth IASTED Int. Conf. Visualization, Imaging and Image Processing, September 2005, Benidorm, Spain, p. 355–359.
-
3)
-
R. Klette ,
K. Schluns ,
A. Koschan
.
(1998)
Computer vision – three-dimensional data from images.
-
4)
-
E.R. Davies
.
(2005)
Machine vision: theory, algorithms, practicalities.
-
5)
-
C. Altera
.
Nios II processor reference handbook.
-
6)
-
K. Muhlmann ,
D. Maier ,
J. Hesser ,
R. Manner
.
Calculating dense disparity maps from color stereo images, an efficient implementation.
Int. J. Comput. Vis.
,
79 -
88
-
7)
-
(2007)
DSP-Builder v. 7.2 reference manual.
-
8)
-
Sunyoto, H., Van Der Mark, W., Gavrila, D.: `A comparative study of fast dense stereo vision algorithms', Proc. 2004 IEEE Intelligent Vehicles Symp., June 2004, Parma, Italy, p. 319–324.
-
9)
-
Y. Miyajima ,
T. Maruyama
.
(2003)
A real-time stereo vision system with FPGA’, in ‘Field programmable logic and applications.
-
10)
-
Maclean, W.J.: `An evaluation of the suitability of FPGAs for embedded vision systems', Proc. 2005 IEEE Computer Society Conf. Computer Vision and Pattern Recognition (CVPR'05), June 2005, San Diego, CA, USA, 3, p. 131–137.
-
11)
-
M. Hariyama ,
Y. Kobayashi ,
H. Sasaki ,
M. Kameyama
.
FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (Japan)
,
12 ,
3516 -
3522
-
12)
-
Kanade, T., Yohsida, A., Oda, K., Kano, H., Tanaka, M.: `A stereo machine for video-rate dense depth mapping and its new applications', Proc. 15th Computer Vision and Pattern Recognition Conference (CVPR), June 1996, San Francisco, USA, p. 196–202.
-
13)
-
J. Batlle ,
J. Marti ,
P. Ridao ,
J. Amat
.
A new FPGA/DSP-based parallel architecture for real-time image processing.
Real-Time Imaging
,
345 -
356
-
14)
-
Woodfill, J.I., Gordon, G., Buck, R.: `Tyzx DeepSea high speed stereo vision system', Computer Vision and Pattern Recognition Workshop, June 2004, Washington, DC, USA, p. 41.
-
15)
-
J. Kalomiros ,
J. Lygouras
.
Design and evaluation of a hardware/software architecture for fast image processing.
Microprocess. Microsyst.
-
16)
-
B. Kang ,
K. Woo ,
Ch. Hong ,
D. Hong ,
H. Yang
.
Design of three-dimensional real-time system using stereo images.
Curr. Appl. Phys.
,
31 -
36
-
17)
-
NAC Image Technology web page, available at: http://nacinc.com,accessed January 2008.
-
18)
-
Lee, S., Yi, J., Kim, J.: `Real-time stereo vision on a reconfigurable system', Proc. Fifth Int. Workshop on Systems, Architectures, Modeling, and Simulation, July 2005, Samos, Greece, 3553, Springer, Berlin/Heidelberg, p. 299–307, 2005Lecture Notes Series in Computer Science, .
-
19)
-
(2005)
Avalon interface specification.
-
20)
-
Hirschmuller, H.: `Improvements in real-time correlation-based stereo vision', Proc IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV'01), December 2001, p. 141–148.
-
21)
-
Diaz, J., Ros, E., Mota, S., Ortigoza, E.M., Del Pino, B.: `High performance stereo computation architecture', Proc. IEEE Int. Conf. Field Programmable Logic and Applications (FPL'05), August 2005, Tampere, Finland, p. 463–468.
-
22)
-
M.Z. Brown ,
D. Burschka ,
G. Hager
.
Advances in computational stereo.
IEEE Trans. Pattern Anal. Mach. Intell.
,
8 ,
993 -
1008
-
23)
-
Forstmann, S., Kanou, Y., Ohya, J., Thuering, S., Schmitt, A.: `Real-time stereo by using dynamic programming', Proc. 2004 IEEE Computer Society Conf. Computer Vision and Pattern Recognition Workshops (CVPRW'04), June 2004, Washington, DC, USA, 3, p. 29–36.
-
24)
-
Darabiha, A., Rose, J., MacLean, W.J.: `Video-rate depth measurement on programmable hardware', Proc. IEEE Computer Society Conf. Computer Vision and Pattern Recognition (CVPR'03), June 2003, Madison, WI, USA, 1, p. 203–210.
-
25)
-
D. Scharstein ,
R. Szeliski
.
A taxonomy and evaluation of dense two-frame stereo correspondence algorithms.
Int. J. Comput. Vis.
,
7 -
42
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