Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors present a scheduling methodology for conditional execution of kernels onto single instruction stream/multiple data stream multicontext reconfigurable architectures. Data flow graphs are used to describe the target applications in which some kernels are conditionally executed depending on runtime conditions. Immediately after testing a condition the next kernel to be processed is known and its configurations and input data can be loaded, producing a computation stall while these transfers are performed. A compilation-time kernel scheduling is proposed to handle conditional branches (CBs) by determining a kernel sequence that minimises these computation stalls reducing the application latency. Target applications are firstly partitioned taking into account the presence of CBs, and then kernels are ordered for execution and mapped onto the reconfigurable system. Experimental results obtained for interactive and synthetic applications demonstrate the effectiveness of the proposal.

References

    1. 1)
      • Shang, L., Jha, N.: `Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs', Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), January 2002, p. 345–352.
    2. 2)
    3. 3)
      • Miyamori, T., Olukotun, U.: `A quantitative analysis of reconfigurable coprocessors for multimedia applications', Proc. IEEE Symp. FPGAs for Custom Computing Machines, April 1998, p. 2–11.
    4. 4)
    5. 5)
      • Mirsky, E., Dehon, A.: `MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources', Proc. IEEE Symp. FPGAs for Custom Computing Machines, April 1996, p. 157–166.
    6. 6)
    7. 7)
      • M. Sánchez-élez , H. Du , N. Tabrizi . Algorithm optimizations and mapping schemes for interactive ray tracing on a reconfigurable architecture. Comput. Graph. , 5 , 701 - 713
    8. 8)
      • Smit, G., Havinga, P.: `Dynamic reconfiguration in mobile systems', Proc. Int. Conf. Field Programmable Logic and Applications (FPL), September 2002, p. 171–181.
    9. 9)
    10. 10)
      • Narayanan, P.: `Processor autonomy on SIMD architectures', Proc. Int. Conf. Supercomputing (ICS), 1993, p. 127–136.
    11. 11)
      • Chatha, K., Vemuri, R.: `Hardware-software codesign for dynamically reconfigurable architectures', Proc. Int. Conf. Field Programmable Logic and Applications (FPL), LNCS, 1999, 1673, Springer-Verlag, p. 175–185.
    12. 12)
    13. 13)
      • A. Abnous , C. Christensen , J. Gray . Design and implementation of TinyRISC microprocessor. Microprocess. Microsyst. , 4 , 187 - 194
    14. 14)
    15. 15)
      • Li, Z., Hauck, S.: `Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation', Proc. Int. Symp. FPGAs, February 2002, p. 187–195.
    16. 16)
      • Eskinazi, R., Lima, M., Maciel, P.: `A methodology for hardware tasks scheduling optimized in time for partial and dynamic reconfiguration of FPGAs', Proc. Int. Workshop on Applied Reconfigurable Computing (ARC), February 2005, p. 76–83.
    17. 17)
      • Gray, J., Kean, T.: `Configurable hardware: a new paradigm for computation', Proc. Decennial CalTech Conf. VLSI, March 1989, p. 277–293.
    18. 18)
      • Anido, M., Paar, A., Bagherzadeh, N.: `A novel method for improving the operation autonomy of SIMD processing elements', Proc. Symp. Integrated Circuits and Systems Design, 2002, p. 49–54.
    19. 19)
      • F. Randima . (2002) GPU gems: programming techniques, tips and tricks for real-time graphics.
    20. 20)
      • IPFlex Inc. DAPDNA-2 Dynamically reconfigurable processor, http://www.ipflex.com, 2007.
    21. 21)
      • Becker, J., Thomas, A., Vorbach, M.: `An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XXP-/Leon-based architecture integration', Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2003, p. 1120–1121.
    22. 22)
      • `Generic coding of moving pictures and associated audio information (MPEG-2)', ISO/IEC 13818, 1996.
    23. 23)
      • Yang, P., Catthoor, F.: `Dynamic mapping and ordering tasks of embedded real-time systems on multiprocessor platforms', Proc. Software and Compilers for Embedded Systems (SCOPES), LNCS, 2004, 3199, Springer-Verlag, p. 167–181.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20070085
Loading

Related content

content/journals/10.1049/iet-cdt_20070085
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address