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Critical race-free low-power NAND match line content addressable memory tagged cache memory

Critical race-free low-power NAND match line content addressable memory tagged cache memory

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Published

A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64% over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-µm low standby power foundry process demonstrate 3.29 fJ/bit/search CAM tag energy at VDD=0.9 V and nearly 1 GHz operating frequency at VDD=1.75 V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.

Inspec keywords: logic gates; content-addressable storage; integrated circuit design; low-power electronics; microprocessor chips; cache storage

Other keywords: voltage 0.9 V; tagged microprocessor cache; cache design; low-capacitive clock loading; low-power content addressable memory; critical race-free low-power NAND match line; dynamic hierarchical NAND match lines; voltage 1.75 V; tagged cache memory; circuit design; power dissipation savings

Subjects: Associative storage; Memory circuits; Logic circuits; Digital circuit design, modelling and testing; Microprocessors and microcomputers; Semiconductor storage; Logic elements; Microprocessor chips

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