Comparative study of centralised and distributed compatibility-based test data compression
Comparative study of centralised and distributed compatibility-based test data compression
- Author(s): A. Al-Yamani ; N. Devta-Prasanna ; A. Gunda
- DOI: 10.1049/iet-cdt:20070037
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- Author(s): A. Al-Yamani 1 ; N. Devta-Prasanna 2 ; A. Gunda 2
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View affiliations
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Affiliations:
1: KFUPM, Dhahran, Saudi Arabia
2: LSI Logic Corporation, Milpitas, USA
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Affiliations:
1: KFUPM, Dhahran, Saudi Arabia
- Source:
Volume 2, Issue 2,
March 2008,
p.
108 – 117
DOI: 10.1049/iet-cdt:20070037 , Print ISSN 1751-8601, Online ISSN 1751-861X
Analysis of the tradeoff between hardware overhead, runtime and test data volume is presented when implementing systematic scan reconfiguration using centralised and distributed architectures of the segmented addressable scan, which is an Illinois-scan-based architecture. The results show that the centralised scheme offers better data volume compression, similar automatic test pattern generation (ATPG) runtime results and lower hardware overhead. The cost with the centralised scheme is in the routing congestion.
Inspec keywords: automatic test pattern generation; flip-flops; data compression
Other keywords:
Subjects: Logic and switching circuits; Logic circuits; Digital circuit design, modelling and testing; Logic design methods
References
-
-
1)
- Hiraide, T., Boateng, K.O., Konishi, H.: `BIST-aided scan test – a new method for test cost reduction', VLSI Test Symp. (VTS'03), April 2003, p. 359–364.
-
2)
- J. Rajski , J. Tyszer , M. Kassab , N. Mukherjee . Embedded deterministic test. IEEE Trans. Comput.-Aided Des. , 5 , 776 - 792
-
3)
- Xiang, D., Sun, J., Chen, M.: `Cost-effective scan architecture and a test application scheme for scan testing with non-scan test power and test application cost', 20040153978, August 2004.
-
4)
- S. Sharifi , M. Hosseinabadi , P. Riahi , Z. Navabi . Reducing test power, time and data volume in SoC testing using selective trigger scan architecture. Int. Symp. Defect and Fault Tolerance (DFT'03)
-
5)
- K.-J. Lee , J.-J. Chen , C.-H. Huang . Broadcasting test patterns to multiple circuits. IEEE Trans. Comput.-Aided Design , 12 , 1793 - 1802
-
6)
- G. De Micheli . (1994) Synthesis and optimization of digital circuits.
-
7)
- Ando, H.: `Testing VLSI with random access scan', IEEE Computer Society Conf. (COMPCON'80), February 1980, p. 50–52.
-
8)
- E. McCluskey . (1986) Logic design principles with emphasis on testable semicustom circuits.
-
9)
- E.J. McCluskey , D. Burek , B. Koenemann . Test data compression. Des. Test Comput. , 2 , 76 - 87
-
10)
- P. Rosinger , B.M. Al-Hashimi , N. Nicolici . Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. Comput. Aided Des. , 7 , 1142 - 1153
-
11)
- Mitra, S., Kim, K.: `XMAX: X-tolerant architecture for MAXimal test compression', Int. Conf. Computer Design (ICCD'03), October 2003, p. 326–330.
-
12)
- Sinanoglu, O., Orailoglu, A.: `A novel scan architecture for power-efficient, rapid test', Int. Conf. Computer-Aided Design (ICCAD'02), November 2002, p. 299–303.
-
13)
- Koenemann, B.: `LFSR-coded test patterns for scan designs', European Test Conf. (ETC'91), 1991, p. 237–242.
-
14)
- Samaranayake, S., Gizdarski, E., Sitchinava, N.: `A reconfigurable shared scan-in architecture', VLSI Test Symp. (VTS'03), April 2003.
-
15)
- T.-C. Huang , K.-J. Lee . A token scan architecture for low power testing. Int. Test Conf. (ITC'01) , 660 - 669
-
16)
- Al-Yamani, A., Chmelar, E., Grinchuk, M.: `Segmented addressable scan architecture', VLSI Test Symp., May 2005, (VTS'05).
-
17)
- Baik, D.H., Saluja, K.K., Kajihara, S.: `Random access scan: a solution to test power, test data volume, and test time', Int. Conf. VLSI Design (VLSID'04), January 2004, p. 883–888.
-
18)
- Arslan, B., Orailoglu, A.: `Test cost reduction through a reconfigurable scan architecture', Int. Test Conf. (ITC'04), November 2004, p. 945–952.
-
19)
- Al-Yamani, A., Devta-Prasanna, N., Gunda, A.: `Systematic scan reconfiguration', 12thIEEE Asia and South Pacific Design Automation Conf. (ASPDAC'07), 23–26 January 2007, Yokohama, Japan.
-
20)
- Al-Yamani, A., McCluskey, E.J.: `Seed encoding for LFSRs and cellular automata', 40thDesign Automation Conf. (DAC'03), June 2003.
-
21)
- Arslan, A., Orailoglu, A.: `CircularScan: a scan architecture for test cost reduction', Design, Automation and Test in Europe Conf. and Exhibition (DATE'04), February 2004, 2, p. 1290–1295.
-
22)
- Lay, L., Patel, J., Rinderknecht, T.: `Logic BIST with scan chain segmentation', Int. Test Conf. (ITC'04), November 2004, p. 57–66.
-
23)
- Oh, N., Kapur, R., Williams, T.: `Test pattern compression using prelude vectors in fan-out scan chain with feedback architecture', Design, Automation, and Test in Europe Conf. (DATE'03), 2003, p. 110–115.
-
24)
- Hamzaoglu, I., Patel, J.: `Reducing test application time for full scan embedded cores', IEEE Int. Symp. Fault Tolerant Computing (FTC'99), 1999, p. 260–267.
-
1)