Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Test data compression for system-on-a-chip using extended frequency-directed run-length code

Test data compression for system-on-a-chip using extended frequency-directed run-length code

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

One of the major challenges in testing a system-on-a-chip is dealing with the large volume of test data. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0s. It is demonstrated that higher test data compression can be achieved based on encoding both runs of 0s and 1s. An extension to the FDR code is proposed and by experimental results its effectiveness in achieving a higher compression ratio is demonstrated.

Inspec keywords: system-on-chip; data compression; variable length codes; logic testing; runlength codes

Other keywords: system-on-chip testing; variable-to-variable run length code; extended frequency-directed run-length code; data compression

Subjects: Codes; Digital circuit design, modelling and testing; Microprocessor chips; Logic design methods; Microprocessors and microcomputers

References

    1. 1)
      • I. Bayraktaroglu , A. Orailoglu . Concurrent application of compaction and compression for test time and data volume reduction in scan designs. IEEE Trans. Comput. , 11 , 1480 - 1489
    2. 2)
      • A. El-Maleh , Y. Osais . Test vector decomposition based static compaction algorithms for combinational circuits. ACM Trans. Des. Autom. Electron. Syst. , 4 , 430 - 459
    3. 3)
      • Li, L., Chakrabarty, K.: `Test data compression using dictionaries with fixed length indices', Proc. VLSI Test Symp., April 2003, Napa Valley, CA, p. 219–224.
    4. 4)
      • Gonciari, P., Al-Hashimi, B., Nicolici, N.: `Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression', Proc. Design Automation Test in Europe, March 2002, Paris, France, p. 604–611.
    5. 5)
      • M. Nourani , M. Tehranipour . RL-Huffman encoding for test compression and power reduction in scan application. ACM Trans. Des. Autom. Electron. Syst. , 1 , 91 - 115
    6. 6)
      • M. Tehranipour , M. Nourani , K. Chakrabarty . Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans. Very Large Scale Integr. Syst. , 6 , 719 - 731
    7. 7)
      • Reddy, S.M., Pomeranz, I., Kajihara, S.: `On the effects of test compaction on defect coverage', Proc. IEEE VLSI Test Symp., April 1996, Princeton, NJ, p. 430–435.
    8. 8)
      • P.T. Gonciari , B. Al-Hashimi , N. Nicolici . Synchronization overhead in SoC compressed test. IEEE Trans. Very Large Scale Integr. Syst. , 1 , 140 - 153
    9. 9)
      • El-Maleh, A., Al Zahir, S., Khan, E.: `A geometric-primitives-based compression scheme for testing system-on-chip', Proc. VLSI Test Symp., Marina', April 2001, Del Rey, CA, p. 54–59.
    10. 10)
      • P. Wohl , J.A. Waicukauski , S. Patel . Efficient compression of deterministic patterns into multiple PRPG seeds.
    11. 11)
      • A. Chandra , K. Chakrabarty . A unified approach to reduce SoC test data volume, scan power, and testing time. IEEE Trans. Comput. Aided Des. , 3 , 352 - 363
    12. 12)
      • Iyengar, V., Chakrabarty, K., Murray, B.: `Built-in self testing of sequential circuits using precomputed test sets', Proc. VLSI Test Symp., April 1998, Princeton, NJ, p. 418–423.
    13. 13)
      • Y. Zorian , E. Marinissen , S. Dey . Testing embedded-core-based system chips. Comput. Mag. , 6 , 52 - 60
    14. 14)
      • Samaranayake, S., Gizdarski, E., Sitchinava, N.: `A reconfigurable shared scan-in architecture', Proc. 21 VLSI Test Symp., April 2003, Napa Valley, CA, p. 9–14.
    15. 15)
      • El-Maleh, A., Al-Abaji, R.: `Extended frequency-directed run length code with improved application to system-on-a-chip test data compression', Proc. 9th IEEE Int. Conf. Electronics, Circuits and Systems, September 2002, Dubrovnik, Croatia, p. 449–452.
    16. 16)
      • Sitchinava, N., Gizdarski, E., Samaranayake, S.: `Changing the scan enable during shift', Proc. 22nd VLSI Test Symp., April 2004, Napa Valley, CA, p. 73–78.
    17. 17)
      • Semiconductor industry association, international technology roadmap for semiconductors 2001 Edn. http://www.itrs.net/Links/2001ITRS/Home.htm, accessed on 15th January 2007.
    18. 18)
      • Wunderlich, H.-J., Kiefer, G.: `Bit-flipping BIST', Proc. Int. Test Conf., October 1996, Washington, DC, p. 337–343.
    19. 19)
      • Vranken, H., Hapke, F., Rogge, S.: `ATPG padding and ATE vector repeat per port for reducing test data volume', Proc. Int. Test Conf., September 2003, Charlotte, NC, p. 1069–1078.
    20. 20)
      • Ma, S.C., Franco, P., McCluskey, E.J.: `An experimental chip to evaluate test techniques experimental results', Proc. Int. Test Conf., October 1995, Washington, DC, p. 663–672.
    21. 21)
      • Pomeranz, I., Reddy, L., Reddy, S.: `COMPACTEST: a method to generate compact test sets for combinational circuits', Proc. Int. Test Conf., October 1991, Nashville, TN, p. 194–203.
    22. 22)
      • Jas, A., Touba, N.: `Test vector decompression via cyclical scan chains and its application to testing core-based designs', Proc. Int. Test Conf., October 1998, Washington, DC, p. 458–464.
    23. 23)
      • A. Chandra , K. Chakrabarty . Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans. Comput. , 8 , 1076 - 1088
    24. 24)
      • Jas, A., Ghosh-Dastidar, J., Touba, N.: `Scan vector compression/decompression using statistical coding', Proc. VLSI Test Symp., April 1999, San Diego, CA, p. 114–120.
    25. 25)
      • J. Rajski , J. Tyszer , M. Kassab , N. Mukherjee . Embedded deterministic test. IEEE Trans. Comput.-Aided Des. , 5 , 776 - 792
    26. 26)
      • Hamzaoglu, I., Patel, J.H.: `Test set compaction algorithms for combinational circuits', Proc. Int. Conf. Computer-Aided Design, November 1998, San Jose, California, p. 283–289.
    27. 27)
      • Wang, L.-T., Xiaoqing, W., Furukawa, H.: `VirtualScan: a new compressed scan technology for test cost reduction', Proc. Int. Test Conf., October 2004, Charlotte, NC, p. 916–925.
    28. 28)
      • Wurtenberger, A., Tautermann, C., Hellebrand, S.: `A hybrid coding strategy for optimized test data compression', Proc. Int. Test Conf, Sep 2003, Charlotte, NC, p. 451–459.
    29. 29)
      • El-Maleh, A., Al-Suwaiyan, A.: `An efficient test relaxation technique for combinational and full-scan sequential circuits', Proc. VLSI Test Symp., April 2002, Monterey, CA, p. 53–59.
    30. 30)
      • El-Maleh, A., Al-Utaibi, K.: `An efficient test relaxation technique for synchronous sequential circuits', Proc. VLSI Test Symp., April 2003, Napa Valley, CA, p. 179–185.
    31. 31)
      • Hellebrand, S., Linag, H., Wunderlich, H.-J.: `A mixed-mode BIST scheme based on reseeding of folding counters', Proc. Int. Test Conf., October 2000, Atlantic City, NJ, p. 778–784.
    32. 32)
      • K. Miyase , S. Kajihara . Don't care identification of test patterns for combinational circuits. IEEE Trans. Comput. Aided Des. , 2 , 321 - 326
    33. 33)
      • J. Chang , C. Lin . Test set compaction for combinational circuits. IEEE Trans. Comput. Aided Des. , 11 , 1370 - 1378
    34. 34)
      • P. Rosinger , P. Gonciari , B. Al-Hashimi , N. Nicolici . Simultaneous reduction in volume of test data and power dissipation for system-on-a chip. Electron. Lett. , 24 , 1434 - 1436
    35. 35)
      • A. Jas , J. Gosh-Dastidar , M. Ng , N. Touba . An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. Comput. Aided Des. , 6 , 797 - 806
    36. 36)
      • Touba, N., McCluskey, E.: `Altering a pseudo-random bit sequence for scan based BIST', Proc. Int. Test Conf., October 1996, Washington, DC, p. 167–175.
    37. 37)
      • A. Chandra , K. Chakrabarty . System-on-a-chip data compression and decompression architecture based on Golomb codes. IEEE Trans. Comput. Aided Des. , 3 , 355 - 368
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20070028
Loading

Related content

content/journals/10.1049/iet-cdt_20070028
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address