Hardware architecture for high-speed real-time dynamic programming applications

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Hardware architecture for high-speed real-time dynamic programming applications

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A novel hardware architecture for performing the core computations required by dynamic programming (DP) techniques is introduced. The latter pertain to a vast range of applications that necessitate an optimal sequence of decisions to be obtained. An underlying assumption is that a complete model of the environment is provided, whereby the dynamics are governed by a Markov decision process. Existing DP implementations have traditionally focused on software-based mechanisms. Here, the authors present a method for exploiting the inherent parallelism associated with computing both the value function and optimal policy. This allows for the optimal policy to be obtained several orders of magnitude faster than traditional software implementations, establishing the viability of the approach for demanding, real-time applications. The well-known rental car management problem has been studied as a benchmark for which a field-programmable gate array-based implementation was designed. The results highlight the advantages of the proposed approach with respect to the execution speed and the scalability properties.

Inspec keywords: field programmable gate arrays; Markov processes; mathematics computing; rental; real-time systems; dynamic programming

Other keywords: software-based mechanisms; Markov decision process; hardware architecture; field-programmable gate array; real-time applications; high-speed real-time dynamic programming; rental car management

Subjects: Markov processes; Optimisation techniques; Logic and switching circuits; Mathematics computing

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