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Exploiting parallelism in configurable architectures through custom array mapping

Exploiting parallelism in configurable architectures through custom array mapping

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Configurable architectures offer the unique opportunity of customising the storage allocation to meet specific applications' needs. A compiler approach to map the arrays of a loop-based computation to internal memories of a configurable architecture with the objective of minimising the overall execution time is described. An algorithm that considers the data access patterns of the arrays along the critical path of the computation as well as the available storage and memory bandwidth is presented. Experimental results are presented which demonstrate the application of this approach for a set of kernel codes when targeting a field-programmable gate-array. The results reveal that the proposed algorithm outperforms the naive and custom data layout techniques by an average of 33% and 15% in terms of execution time, while taking into account the available hardware resources.

Inspec keywords: storage allocation; field programmable gate arrays; reconfigurable architectures; parallel architectures; memory architecture

Other keywords: configurable architecture; field-programmable gate-array; kernel codes; data access pattern; parallel architecture; custom array mapping; storage allocation; internal memory; memory bandwidth; parallelism; loop-based computation

Subjects: Memory circuits; Storage system design; Parallel architecture; Logic and switching circuits; Logic circuits; File organisation

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