© The Institution of Engineering and Technology
With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internetbased applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binarycoded decimal (BCD) encoding. The BCDdigit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCDdigit multiplier produces a twoBCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.
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