Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Comparative analysis of GALS clocking schemes

Comparative analysis of GALS clocking schemes

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Because of the increase in complexity of distributing a global clock over a single die, globally asynchronous and locally synchronous systems are becoming an efficient alternative technique to design distributed system-on-chip (SOC). A number of independently clocked synchronous domains can be integrated by clock pausing, clock stretching or data-driven clocking techniques. Such techniques are applied on point-to-point inter-domain communication schemes. Presented here is a comparison of these schemes and how they can be applied to an existing partitioned synchronous architecture to obtain a reliable, low-latency and efficient clock control architectures. The comparison highlights the advantages and disadvantages of one scheme over the other in terms of logical correctness, circuit implementation, performance and relative power consumption. Also presented are circuit solutions for stretchable and data-driven clocking schemes. These circuit solutions can be easily plugged into existing partitioned synchronous islands. To enable early evaluation of functional correctness, also proposed is the use of Petri net modelling techniques to model the asynchronous control blocks that constitute the interface between the synchronous islands.

References

    1. 1)
      • Moore, S.W., Taylor, G.S., Mullins, R.D., Robinson, P.: `Point-to-Point GALS Interconnect', Proc. Int. symp. Asynchronous Circuits and Systems, April 2002, p. 769–775.
    2. 2)
      • Naffziger, S.: `The implementation of a 2-core multi-threaded itanium family processor', Proc. ISSCC, February 2005, p. 182–183.
    3. 3)
    4. 4)
      • Mullins, R., Moore, S.W.: `Demystifying data-driven and pausible clocking schemes', Proc. UK Asynchronous Forum, 2006, Newcastle, UK.
    5. 5)
      • Bormann, D.S., Cheung, P.Y.K.: `Asynchronous wrapper for heterogeneous systems', Proc. ICCD, 1997, p. 307–314.
    6. 6)
      • I.E. Sutherland . Micropipelines. Commun. ACM , 6 , 720 - 738
    7. 7)
      • Khomenko, V.: `Model checking based on prefixes of petri net un-foldings', 2003, PhD, University of Newcastle.
    8. 8)
      • Yun, K., Donhue, R.P.: `Pausible clocking: a first step towards heterogeneous systems', Proc. Int. Conf. Computer Design, October 1996, TX, Austin, p. 118–123.
    9. 9)
      • J. Sparso , J. Sparso , Furber . (2001) Fundamentals, Principles of asynchronous circuit design – a system's perspective.
    10. 10)
      • Krstic, M., Grass, E., Stahl, C.: `Request driven GALS technique for wireless communication systems', Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, March 2005, p. 76–85.
    11. 11)
      • Melzer, S., Römer, S., Esparza, J.: `Verification using PEP', Proc. AMAST, 1996, p. 591–594.
    12. 12)
      • C. Mead , L. Conway . Introduction to VLSI systems.
    13. 13)
      • J. Cortadella , M. Kishinevsky , A. Kondratyev , L. Lavagno , A. Yakovlev . (2002) Logic synthesis of asynchronous controllers and interfaces.
    14. 14)
      • Kessels, J., Peeters, A., Wielage, P., Kim, S.: `Clock synchronization through handshake signalling', Proc. Int. Symp. Asynchronous Circuits and Systems, April 2002, p. 59–68.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20060159
Loading

Related content

content/journals/10.1049/iet-cdt_20060159
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address