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Dynamic global security-aware synthesis using SystemC

Dynamic global security-aware synthesis using SystemC

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A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

References

    1. 1)
      • Kocher, P., Jaffe, J., Jun, B.: `Differential power analysis', Proc. Advances in Cryptology (CRYPTO 1999), LCNS, 1999, p. 388–397.
    2. 2)
      • Biham, E., Shamir, A.: `Differential fault analysis of secret key cryptosystems', Advances in Cryptology – Proc. CRYPTO '97, 1997, p. 513–525.
    3. 3)
      • G. Bertoni , L. Breveglieri , I. Kohen , P. Maistri , V. Piuri . Error analysis and detection procedures for a hardware implementation of the advanced encryption standard. IEEE Trans. Comput , 4 , 492 - 505
    4. 4)
      • C. Yen , B. Wu . Simple error detection methods for hardware implementation of the advanced encryption standard. IEEE Trans. Comput , 6 , 720 - 731
    5. 5)
      • Benini, L., Macii, A., Macii, E., Omerbegovic, E., Poncino, M., Pro, F.: `Energy-aware design techniques for differential power analysis protection', Proc. Design Automation Conf. (DAC), 2003, p. 36–41.
    6. 6)
      • S. Danil , M. Julian , B. Alexander , Y. Alex . Design and analysis of dual-rail circuits for security applications. IEEE Trans. Comput. , 4 , 449 - 460
    7. 7)
      • Tiri, K., Verbauwhede, I.: `A VLSI design flow for secure side-channel attack resistant ICs', Proc. Design Automation and Test in Europe (DATE), 2005, p. 58–63.
    8. 8)
      • Aigner, M., Mangard, S., Menichelli, F., Menicocci, R., Olivieri, M.: `Side channel analysis resistant design flow', Proc. ISCAS, 2006, p. 2909–2912.
    9. 9)
      • Schulz-Key, A., Winterholer, C., Schweizer, M., Kuhn, T., Rosenstiel, W.: `Object-oriented modelling and synthesis of SystemC specifications', Proc. Asia South Pacific Design Automation Conf. (ASPDAC'04), 2004, Yokohama, Japan, p. 238–243.
    10. 10)
      • Bjerregaard, T., Mahaderan, S., Sparso, J.: `A channel library for asynchronous circuit design supporting mixed-mode modelling', Proc. Int. Workshop on Power and Time Modelling, Optimization and Simulation (PATMOS), 2004, Springer, p. 301–310.
    11. 11)
      • S. Devadas , A. Newton . Algorithms for hardware allocation in data path synthesis. IEEE Trans. CAD , 768 - 781
    12. 12)
      • K. Jensen . (1997) Coloured Petri nets. Basic concepts, analysis methods and practical use’, Volume 1, Basic concepts. EATCS Monographs in theoretical computer science.
    13. 13)
      • Shang, D., Xia, F., Yakovlev, A.: `Asynchronous circuit synthesis via direct translation', Proc. ISCAS, Scottsdale, Arizona, 2002, p. 369–372.
    14. 14)
      • Moore, S., Anderson, R., Cunningham, P., Mullins, R., Taylor, G.: `Improving smart card security using self-timed circuits', ASYNC'02, 2002, p. 114–125.
    15. 15)
      • Tiri, K., Verbauwhede, I.: `Design method for constant power consumption of differential logic circuits', Proc. Design Automation and Test in Europe (DATE), 2005, p. 628–633.
    16. 16)
      • S. Mangard , M. Aigner , S. Dominikus . A highly regular and scalable AES hardware architecture. IEEE Trans. Comput. , 4 , 483 - 491
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