Finite state machine-based DRAM power management with early resynchronisation

Finite state machine-based DRAM power management with early resynchronisation

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An efficient operating system-based power management scheme for DRAM in the multiprogramming/time-sharing environment is presented. Formulas for evaluating the condition of positive energy gain are developed and a finite state machine (FSM) for selecting the best power mode for a given idle time is designed. In the proposed scheme, the scheduler selectively assigns the most efficient power mode to each idle memory bank at context switching time based on the FSM. For computing the idle time, two efficient and practical prediction methods are developed and tested for performance. The proposed scheme achieves further energy saving by starting the resynchronisation of idle memory banks as early as possible. In the aspects of the prediction method and the early resynchronisation method, multiple versions of the proposed scheme are developed and tested for performance. The proposed scheme utilises events occurring at context switching time in the multiprogramming/time-sharing environment and the scheduling ensures the maximum energy gain without significantly degrading the performance. The proposed scheme is tested with a simulated system, and the experimental results demonstrate the efficiency of the scheme. In the experiment, the energy gain by using the proposed scheme ranges from 17.84% to 52.21% depending on the time quantum sizes tested.


    1. 1)
      • C. Lefurgy , K. Rajamani , F. Rawson , W. Felter , M. Kistler , T.W. Keller . Energy management for commercial servers. IEEE Comput. , 12 , 39 - 48
    2. 2)
      • Li, X., Li, Z., David, F., Zhou, P., Zhou, Y., Adve, S., Kumar, S.: `Performance directed energy management for main memory and disks', Proc. 13th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS'04), October 2004, Boston, MA, USA.
    3. 3)
      • P.W. Diodato . Embedded DRAM: more than just a memory. IEEE Comput. Mag. , 118 - 126
    4. 4)
      • S.S. Iyer , H.L. Kalter . (1999) Embedded DRAM technology.
    5. 5)
      • Puttaswamy, K., Choi, K.-W., Park, J.C., Mooney, V.J., Chatterjee, A., Ellervee, P.: `System level power-performance trade-offs in embedded systems voltage and frequency scaling of off-chip buses and memory', Proc. IEEE/ACM Int. Symposium on System Synthesis (ISSS'2002), October 2002, Tokyo, Japan, p. 225–230.
    6. 6)
      • W.-T. Shiue , S. Udayanarayanan , C. Chakrabarti . Data memory design and exploration for low-power embedded systems. ACM Trans. Des. Autom. Electron. Syst. , 4 , 553 - 568
    7. 7)
      • Y.-J. Chang , F. Lai . Dynamix zero-sensitivity scheme for low-power cache memories. IEEE Micro , 4 , 20 - 32
    8. 8)
      • Y.-J. Chang , S.-J. Ruan , F. Lai . Design and analysis of low-power cache using two-level filter scheme. IEEE Trans. VLSI Syst. , 568 - 580
    9. 9)
      • K. Inoue , A.G. Moshnyaga , K. Murakami . Trends in high-performance, low-power cache memory architectures. IEICE Trans. Electron. , 2 , 304 - 314
    10. 10)
      • Irwin, M.J., Narayanan, V.: `Low power design: from soup to nuts', Int. Symp. on Computer Architecture (ISCA'2000), Tutorial, 2000.
    11. 11)
      • Y. Meng , T. Sherwood , R. Kastner . Exploring the limits of leakage power reduction in caches. ACM Trans. Archit. Code Optim. , 221 - 246
    12. 12)
      • Shiue, W.-T., Chakrabarti, C.: `Memory exploration for low power, embedded systems', Proc. 36th Design and Automation Conf. (DAC'99), June 1999, New Orleans, LA, USA, p. 250–253.
    13. 13)
      • C. Zhang , F. Vahid , J. Yang , W. Najjar . A way-halting cache for low-energy high-performance systems. ACM Trans. Archit. Code Optim , 34 - 54
    14. 14)
      • Zhu, Y., Mueller, F.: `Preemption handling and scalability of feedback DVS-EDF', Proc. Workshop on Compilers and Operating Systems for Low Power (COLP'02), September 2002.
    15. 15)
      • Benini, L., Macii, A., Macii, E., Poncino, M.: `Synthesis of application-specific memories for power optimization in embedded systems', Proc. 37th Design Automation Conf. (DAC'2000), June 2000, Los Angeles, CA, USA, p. 300–303.
    16. 16)
      • Benini, L., Macii, A., Poncino, M.: `A recursive algorithm for low-power memory partitioning', Proc. 2000 Int. Symposium on Low Power Electronics and Design (ISLPED'00), July 2000, Rapallo, p. 78–83, Italy.
    17. 17)
      • Cao, Y., Tomiyama, H., Okuma, T., Yasuura, H.: `Data memory design considering effective bitwidth for low-energy embedded systems', Proc. IEEE/ACM Int. Symposium on System Synthesis (ISSS'2002), October 2002, Tokyo, Japan, p. 201–206.
    18. 18)
      • W.-C. Cheng , M. Pedram . Power-optimal encoding for a DRAM address bus. IEEE Trans. VLSI Syst. , 2 , 109 - 118
    19. 19)
      • Delaluz, V., Kandemir, M., Vijaykrishnan, N., Sivasubramaniam, A., Irwin, M.J.: `DRAM energy management using software and hardware directed power mode control', Proc. Int. Symp. on High Performance Computer Architecture (HPCA-7), January 2001, Monterrey, Mexico, p. 159–169.
    20. 20)
      • Delaluz, V., Sivasubramaniam, A., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: `Scheduler-based DRAM energy management', Proc. 39th Design Automation Conf. (DAC'2002), June 2002, New Orleans, LA, USA, p. 697–702.
    21. 21)
      • Fan, X., Ellis, C., Lebeck, A.R.: `Memory controller policies for DRAM power management', Proc. 2001 Int. Symposium on Low Power Electronics and Design (ISLPED'01), August 2001, Huntington Beach, CA, USA, p. 129–134.
    22. 22)
      • Fan, X., Ellis, C., Lebeck, A.R.: `Modeling of DRAM power control policies using deterministic and stochastic petri nets', Proc. Workshop on Power-Aware Computer Systems, February 2002.
    23. 23)
      • Lebeck, R., Fan, X., Zeng, H., Ellis, C.: `Power aware page allocation', Proc. 9th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS'00), November 2000, Cambridge, MA, USA, p. 105–116.
    24. 24)
      • Tadonki, C., Rolim, J.: `An analytical model for energy minimization', Proc. 3rd Int. Workshop on Experimental and Efficient Algorithms, May 2004, 3059/2004, Lecture Notes in Computer Science, p. 559–569.
    25. 25)
      • Udayakumaran, S., Narahari, B., Simha, R.: `Application-specific memory partitioning for low power consumption', Proc. Workshop on Compiler and Operating Systems for Low Power (COLP'02), September 2002.
    26. 26)
      • Rambus Inc.:,accessed 2006.
    27. 27)
      • Dalton, B., Ellis, C.S.: `Sensing user intention and context for energy management', Proc. 9th Workshop on Hot Topics in Operating Systems, May 2003.
    28. 28)
      • Jha, N.K.: `Low power system scheduling and synthesis', Proc. 2001 Int. Conf. on Computer-Aided Design (ICCAD'01), November 2001, San Jose, CA, USA, p. 344–352.
    29. 29)
      • Lu, Y.-H., Benini, L., Micheli, G.D.: `Operating-system directed power reduction', Proc. Int. Symp. on Low Power Electronics and Design (ISLPED'00), July 2000, Rapallo, Italy, p. 37–42.
    30. 30)
      • Y.-H. Lu , L. Benini , G.D. Micheli . Power-aware operating systems for interactive systems. IEEE Trans. VLSI Syst. , 2 , 119 - 134
    31. 31)
      • Y.-H. Lu , G.D. Micheli . Comparing system-level power management policies. IEEE Des. Test Comput. , 10 - 19
    32. 32)
      • Nathuji, R., Seshasayee, B., Schwan, K.: `Combining compiler and operating system support for energy efficient I/O on embedded platforms', Proc. 2005 Workshop on Software and Compilers for Embedded Systems, 2005, p. 80–90.
    33. 33)
      • T. Okuma , T. Ishihara , H. Yasuura . Software energy reduction techniques for variable-voltage processors. IEEE Des. Test Comput. , 31 - 41
    34. 34)
      • Yuan, W., Nahrstedt, K.: `Energy-efficient soft real-time CPU scheduling for mobile multimedia systems', Proc. 19th ACM Symp. on Operating Systems Principles (SOSP'03), October 2003, Bolton Landing, NY, USA, p. 149–163.
    35. 35)
      • Zeng, H., Ellis, C.S., Lebeck, A.R., Vahdat, A.: `Currentcy: a unifying abstraction for expressing energy management policies', Proc. Usenix Annual Technical Conf., 2003, p. 43–56.
    36. 36)
      • Zhu, Q., Shankar, A., Zhou, Y.: `PB-LRU: a self-tuning power aware storage cache replacement algorithm for conserving disk energy', Proc. 18th Annual Int. Conf. on Supercomputing (ICS'04), June 2004, Malo, France, p. 79–88.
    37. 37)
      • Gries, M.: `The impact of recent DRAM architectures on embedded systems performance', Proc. 26th EUROMICRO Conf. (EUROMICRO'00), September 2000, Maastricht, the Netherlands, p. 282–289.
    38. 38)
      • Rambus Inc.: Rambus: Desktop Performance for Mobile PCs,, accessed February, 2007.
    39. 39)
      • B. Jacob Vinodh , B. Davis , T. Mudge . High performance DRAMs in workstation environments. IEEE Trans. Comput. , 11 , 1133 - 1153
    40. 40)
      • Fan, X., Ellis, C., Lebeck, A.R.: `The synergy between power-aware memory systems and processor voltage scaling', Proc. Workshop on Power-Aware Computer Systems, December 2003.

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