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Towards a configurable SoC MPEG-4 advanced simple profile decoder

Towards a configurable SoC MPEG-4 advanced simple profile decoder

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The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques are applied to the advanced simple profile of an MPEG-4 decoder, for which an innovative SystemC-based system-level design tool, called CASSE, has been used. Simulations results showed that a throughput of 15 QCIF frames per second can be achieved with a low area and low power implementation. Details of this implementation and where the results differ from simulation are presented.

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