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Modern field programmable gate array (FPGA) architectures are moving towards heterogeneity with the increasing inclusion of coarse grained elements such as embedded multipliers and RAMs. This has given rise to a multi-dimensioned resource-based measure of design area, very different from the traditional application-specific integrated circuit figure of silicon area. In order for a designer to use these heterogenous elements in their design, they must usually specifically instantiate them. Heterogeneous elements not used in a design remain unused on the device, consuming leakage power, silicon area and manufacturing costs. Method of transferring functionality normally implemented in embedded ROMs and 4-input look-up tables (4-LUTs) onto unused digital signal processor (DSP) blocks is proposed. The paper proceeds to include this method in a synthesis system incorporating the idea of resource constrained synthesis, where a design is mapped to an FPGA considering user and device constraints on heterogenous element usage, based on an extension to the Altera Quartus II synthesis software. Results have been obtained, showing an improvement over existing methods in 76% of the 21 ROMs examined. Further results have been obtained from applying this approach with the synthesis system to benchmark algorithms. In the designs examined, the number of possible implementations has increased by two to four times over Altera Quartus.
References
-
-
1)
-
R.K. Gupta ,
Y. Zorian
.
Introducing core-based system design.
IEEE Des. Test Comput.
,
4 ,
15 -
25
-
2)
-
M. Hutton ,
J. Scleicher ,
D. Lewis ,
B. Pedersen ,
R. Ynan ,
S. Kaptanoglu ,
J. Becker ,
M. Platzner ,
S. Vernalde
.
(2004)
Improving FPGA performance and area using an adaptable logic module, Proceedings of the Field programmable logic.
-
3)
-
Defour, D., de Dinechin, F., Muller, J.: `A new scheme for table-based evaluation of functions', Proc. 36th Conf. on Signals Syst. Comput., 2002.
-
4)
-
Schulte, M., Stine, J.: `Symmetric bipartite tables for accurate function approximation', Proc. 13th IEEE Symp. on Comp. Arith., 1997.
-
5)
-
Morris, G.W.: `Migrating functionality from ROMs to embedded multipliers', MPhil/PhD Transfer Report, 2004.
-
6)
-
Xilinx CORE Generator Guide Xilinx 1994–2002.
-
7)
-
J. Muller
.
A few results on table-based methods.
Reliable Computing
,
3 ,
279 -
288
-
8)
-
Aravena, J., Soh, S.: `Architectures for polynomial evaluation', Proc. 21st Southeastern Symp. on System Theory, 1989.
-
9)
-
de Dinechin, F., Tisserand, A.: `Some improvements on multipartite table methods', Proc. 15th IEEE Symp. on Comp. Arith., 2001.
-
10)
-
Murgai, R.: `Logic synthesis for field-programmable gate arrays', 1993, PhD, University of California at Berkeley, Thesis.
-
11)
-
N. Metropolis ,
A. Rosenbluth ,
M. Rosenbluth ,
A. Teller ,
E. Teller
.
Equation of state calculations by fast computing machines.
J. Chem. Phys.
,
1087 -
1092
-
12)
-
T. Pavlidis ,
A. Maika
.
Uniform piecewise polynomial approximation with variable joints.
J. Approx. Theory
,
61 -
69
-
13)
-
S. Wilton
.
Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays.
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
,
1 ,
56 -
68
-
14)
-
DasSarma, D., Matula, D.: `Faithful bipartite ROM reciprocal tables', Proc. 12th IEEE Symp. on Comp. Arith., 1995.
-
15)
-
Wilton, S.: `Implementing logic in FPGA memory arrays: heterogeneous memory architectures', Proc. IEEE Int. Conf. on Field-Programmable Technology, 2002.
-
16)
-
D. Andrews ,
D. Niehaus ,
P. Ashenden
.
Programming models for hybrid CPU/FPGA chips.
IEEE Comput.
,
1 ,
118 -
120
-
17)
-
Altera Corporation, Quartus II University Program (QUIP) Version 2.1, Altera 2004.
-
18)
-
Morris, G.W., Constantinides, G.A., Chenug, P.Y.K.: `Using DSP blocks for ROM replacement: a novel synthesis flow', Proc. Field Programmable Logic, 2005.
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