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Test data truncation for test quality maximisation under ATE memory depth constraint

Test data truncation for test quality maximisation under ATE memory depth constraint

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Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

References

    1. 1)
      • Vranken, H., Hapke, F., Rogge, S., Chindamo, D., Volkrink, E.: `ATPG padding and ATE vector repeat per port for reducing test data volume', Proc. Int. Test Conference (ITC), 2003, Charlotte, NC, USA, p. 1069–1078.
    2. 2)
      • (1999) International Technology Roadmap for Semiconductors (ITRS).
    3. 3)
      • Goel, S.K., Chiu, K., Marinissen, E.J., Nguyen, T., Oostdijk, S.: `Test infrastructure design for the Nexperia', Proc. Design, Automation and Test in Europe Conference (DATE), 2004, Paris, France, p. 1530–1591.
    4. 4)
      • Iyengar, V., Goel, S.K., Marinissen, E.J., Chakrabarty, K.: `Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints', Proc. Int. Test Conference (ITC), October 2002, Baltimore, USA, p. 1159–1168.
    5. 5)
      • McLaurin, T.L., Potter, J.C.: `On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores', Proc. Int. Test Conference (ITC), October 2000, Atlantic City, NJ, USA, p. 1100–1107.
    6. 6)
      • Harrod, P.: `Testing reusable IP–a case study', Proc. Int. Test Conference (ITC), 1999, Atlantic City, NJ, USA, p. 493–498.
    7. 7)
      • Varma, P., Bhatia, S.: `A structured test re-use methodology for core-based system chips', Proc. Int. Test Conference (ITC), October 1998, Washington, DC, USA, p. 294–302.
    8. 8)
      • Marinissen, E.J., Arendsen, R., Bos, G., Dingemanse, H., Lousberg, M., Wouters, C.: `A structured and scalable mechanism for test access to embedded reusable cores', Proc. Int. Test Conference (ITC), October 1998, Washington, DC, USA, p. 284–293.
    9. 9)
      • Iyengar, V., Chakrabarty, K., Marinissen, E.J.: `Test wrapper and test access mechanism co-optimization for system-on-chip', Proc Int. Test Conference (ITC), 2001, Baltimore, MD, USA, p. 1023–1032.
    10. 10)
      • Huss, S.D., Gyurcsik, R.S.: `Optimal ordering of analog integrated circuit tests to minimize test time', Proc. Design Automation Conference (DAC), June 1991, San Francisco, CA, USA, p. 494–499.
    11. 11)
      • L. Milor , A.L. Sangiovanni-Vincentelli . Minimizing production test time to detect faults in analog circuits. IEEE Trans. Computer-Aided Design Integrated Circuits Syst. , 6
    12. 12)
      • W.J. Jiang , B. Vinnakota . Defect-oriented test scheduling. Trans. Very-Large Scale Integration (VLSI) Syst. , 3 , 427 - 438
    13. 13)
      • Larsson, E., Pouget, J., Peng, Z.: `Defect-aware SOC test scheduling', Proc VLSI Test Symposium (VTS), April 2004, Napa Valley, CA, USA, p. 359–364.
    14. 14)
      • El-Maleh, A., Al-Abaji, R.: `Extended frequency-directed run length code with improved application to system-on-a-chip test data compression', Proc. 9th IEEE Int. Conf. Electronics, Circuits and Systems, September 2002, p. 449–452.
    15. 15)
      • P.T. Gonciari , B.M. Al-Hashimi , N. Nicolici . Variable-length input Hoffman coding for system-on-a-chip test. Trans. Computer-Aided Design Integrated Circuits Syst. , 6 , 783 - 796
    16. 16)
      • V. Iyengar , A. Chandra . Unified SOC test approach based on test data compression and TAM design. IEE Proc.-Comput. Digit. Tech. , 1 , 82 - 88
    17. 17)
      • L. Li , K. Chakrabarty . Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans. Design Automation Electron. Syst. , 4 , 470 - 490
    18. 18)
      • M. Tehranipoor , M. Nourani , K. Chakrabarty . Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans. Very Large Scale Integration (VLSI) Syst. , 6 , 719 - 731
    19. 19)
      • Wurtenberger, A., Tautermann, C.S., Hellebrand, S.: `Data compression for multiple scan chains using dictionaries with corrections', Proc. Int. Test Conference (ITC), 2004, Charlotte, NC, USA, p. 926–935.
    20. 20)
      • Ichihara, H., Ogawa, A., Inoue, T., Tamura, A.: `Dynamic test compression using statistical coding', Proc. Asian Test Symposium (ATS), November 2001, Kyoto, Japan, p. 143–148.
    21. 21)
      • A. Chandra , K. Chakrabarty . System-on-a-chip test data compression and decompression architectures based on Golomb codes. Trans. CAD IC. Syst. , 3 , 355 - 367
    22. 22)
      • Iyengar, V., Chakrabarty, K., Murray, B.: `Built-in self-testing of sequential circuits using precomputed test sets', Proc. VLSI Test Symposium (VTS), 1998, Princeton, NJ, USA, p. 418–423.
    23. 23)
      • Chandra, A., Chakrabarty, K.: `Frequency-directed-run-length (FDR) codes with application to system-on-a-chip test data compression', Proc. VLSI Test Symposium (VTS), April 2001, Marina Del Rey, CA, USA, p. 42–47.
    24. 24)
      • Volkerink, E.H., Khoche, A., Mitra, S.: `Packet-based input test data compression techniques', Proc. Int. Test Conference (ITC), October 2002, Baltimore, MD, USA, p. 154–163.
    25. 25)
      • Lin, X., Rajski, J., Pomeranz, I., Reddy, S.: `On static compaction and test pattern ordering for scan designs', Proc. Int. Test Conference, 2001, p. 1088–1098.
    26. 26)
      • El-Maleh, A., Osais, Y.: `On test vector reordering for combinational circuits', Proc. 16th Int. Conf. Microelectronics, 6–8 December 2004, p. 772–775.
    27. 27)
      • G. Blom . Sannolikhetsteori och statistikteori med tillämpningar. Studentlitteratur
    28. 28)
      • Marinissen, E.J., Iyengar, V., Chakrabarty, K.: `A set of benchmarks for modular testing of SOCs', Proc. Int. Test Conference (ITC), October 2002, Baltimore, MD, USA, p. 519–528.
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