References

• 1. 1)
     • Flottes, M.L., Rouzeyre, B., Vople, L.: `A controller resynthesis based method for improving datapath testability', Proc. Int. Symp. on Circuits and Systems, 2000, p. 346–350.
  2. 2)
     • M. Potkonjak , S. Dey , J.L. Wong . Optimizing designs using the addition of deflection operations.
  3. 3)
     • Lee, H.K., Ha, D.S.: `HOPE: an efficient parallel fault simulator', Proc. Design Automation Conf., 1992, p. 336–340.
  4. 4)
     • N. Nicolici , B. Al-Hashimi , A.D. Brown , A.C. Williams . BIST hardware synthesis for RTL data path based on test compatibility classes. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 11 , 1375 - 1385
  5. 5)
     • Niermann, T.M., Patel, J.H.: `HITEC: A test generation package for sequential circuits', Proc. European Design Automation Conf., 1991, p. 214–218.
  6. 6)
     • Chickermane, V., Patel, J.H.: `A fault oriented partial scan design approach', Proc. Int. Conf. Computer-Aided Design, 1991, p. 400–403.
  7. 7)
     • I. Ghosh , A. Raghunathan , N.K. Jha . Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 9 , 1001 - 1014
  8. 8)
     • Y. Makris , J. Collins , A. Orailoglu . Fast hierarchical test path construction for circuits with DFT-free controller-datapath interfaces. J. Electron. Test., Theory Appl. (JETA) , 29 - 42
  9. 9)
     • Makris, Y., Orailoglu, A.: `Test requirement analysis for low cost hierarchical test path construction', Proc. 11th Asian Test Symp. (ATS'02), 2002, p. 134–139.
  10. 10)
      • Inoue, M., Suzuki, K., Okamoto, H., Fujiwara, H.: `Test synthesis for datapaths using datapath-controller functions', Proc. 12th Asian Test Symp. (ATS'03), 2003, p. 294–299.
  11. 11)
      • S. Dey , M. Potkonjak . Nonscan design-for-testability techniques using RT-level design information. IEEE Trans. Comput.‐Aided Des. , 1488 - 1506
  12. 12)
      • Wada, H., Masuzawa, T., Saluja, K.K., Fujiwara, H.: `Design for strong testability of RTL data paths to provide complete fault efficiency', Proc. 13th Int. Conf. on VLSI Design, 2000, p. 300–305.
  13. 13)
      • Lee, H., Ha, D.: `On the generation of test patterns for combinational circuits', Technical Report 12-93, 1993, Department of Electrical Engineering, Virginia Polytechnic Institute and State University.
  14. 14)
      • Makris, Y., Orailoglu, A.: `DFT guidance through RTL test justification and propagation analysis', Proc. Int. Test Conf. (ITC'98), 1998, p. 668–677.
  15. 15)
      • S. Dey , V. Gangaram , M. Potkonjak . A controller redesign technique to enhance testability of controller-data path circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 2 , 157 - 168
  16. 16)
      • Y. Makris , A. Orailoglu . RTL test justification and propagation analysis for modular designs. J. Electron. Test. Theory Appl. (JETA) , 105 - 120
  17. 17)
      • G. De Micheli . (1994) Synthesis and optimization of digital circuits.
  18. 18)
      • Ravi, S., Lakshminarayana, G., Jha, N.K.: `TAO: regular expression based high-level testability analysis and optimization', Int. Test Conf., 1998, p. 331–340.
  19. 19)
      • Makris, Y., Patel, V., Orailoglu, A.: `Efficient transparency extraction and utilization in hierarchical test', Proc. 19th VLSI Test Symp. (VTS'01), 2001, p. 246–251.
  20. 20)
      • Ohtake, S., Wada, H., Masuzawa, T., Fujiwara, H.: `A non-scan DFT method at register-transfer level to achieve complete fault efficiency', Proc. ASP-DAC, 2000, p. 599–604.
  21. 21)
      • Makris, Y., Collins, J., Orailoglu, A.: `Fast hierarchical test path construction for DFT-free controller-datapath circuits', Proc. 9th Asian Test Symp. (ATS'00), 2000, p. 185–190.
  22. 22)
      • Ravi, S., Ghosh, I., Roy, R.K., Dey, S.: `Controller resynthesis for testability enhancement', Proc. 11th Int. Conf. on VLSI Design, 1998, p. 193–198.