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access icon free Efficient VLSI architectures of lifting based 3D discrete wavelet transform

Discrete wavelet transform (DWT) is widely used in the image and video compression due to its high compression ratio and resolution. This study proposes efficient very large scale integration (VLSI) architectures of lifting based 3D-DWT using (5,3) and (9,7) Daubechies wavelets. The advantage of these proposed architectures is the absence of storage buffer in between the row, column, and temporal processes. Also, five and nine numbers of frames of the 3D signal can be processed in parallel using the proposed (5,3) and (9,7) lifting based DWTs, respectively. Due to this parallelism and the elimination of storage buffers, the throughput of the proposed design is greater than other existing techniques. The authors have implemented all the existing and proposed 3D-DWTs using 45 nm CMOS library with Cadence and Artix-7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. For example, the proposed (9,7) lifting based 3D-DWT achieves 85.4% of improvement in the throughput than the conventional design.


    1. 1)
      • 2. Basiri, M.M.A., Sk, N.M.: ‘An efficient VLSI architecture for convolution based DWT using MAC’. 31th IEEE Int. Conf. on VLSI Design and 17th Int. Conf. on Embedded Systems, Pune, India, January 2017, pp. 271276.
    2. 2)
      • 20. Liu, W., Chen, L., Wang, C., et al: ‘Inexact floating-point adder for dynamic image processing’. 14th IEEE Int. Conf. on Nanotechnology, Toronto, Ontario, Canada, August 2014, pp. 239243.
    3. 3)
      • 14. Biswas, R., Malreddy, S.R., Banerjee, S.: ‘A high-precision low-area unified architecture for lossy and lossless 3D multi-level discrete wavelet transform’, IEEE Trans. Circuits Syst. Video Technol., 2018, 28, (9), pp. 23862396.
    4. 4)
      • 27. Basiri, M.M.A., Sk, N.M.: ‘High performance integer DCT architectures for HEVC’. 30th IEEE Int. Conf. on VLSI Design, Hyderabad, India, January 2017, pp. 121126.
    5. 5)
      • 26. Biswas, R., Malreddy, S.R., Banerjee, S.: ‘Supply and threshold voltage scaling for low power CMOS’, IEEE J. Solid State Circuits, 1997, 32, (8), pp. 12101216.
    6. 6)
      • 4. Basiri, M.M.A., Sk, N.M.: ‘An efficient VLSI architecture for lifting based 1D/2D-discrete wavelet transform’, Microprocess. Microsyst., 2016, 47, pp. 404418.
    7. 7)
      • 16. Chakraborty, A., Chakraborty, D., Banerjee, A.: ‘A memory efficient, high throughput and fastest 1D/3D VLSI architecture for reconfigurable 9/7 & 5/3 DWT filters’. IEEE Int. Conf. on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC), Mysore, India, September 2017, pp. 247253.
    8. 8)
      • 6. Weeks, M., Bayoumi, M.A.: ‘Three-dimensional discrete wavelet transform architectures’, IEEE Trans. Signal Process., 2002, 50, (8), pp. 20502063.
    9. 9)
      • 25. Flynn, M.J., Luk, W.: ‘Computer system design: system-on-chip’ (Wiley Publications, USA, 2011), pp. 3971.
    10. 10)
      • 12. Mohanty, B.K., Meher, P.K.: ‘Memory-efficient architecture for 3-D DWT using overlapped grouping of frames’, IEEE Trans. Signal Process., 2011, 59, (11), pp. 56055616.
    11. 11)
      • 24. Fournely, M., Petit, Y., Wagnac, E., et al: ‘High-speed video analysis improves the accuracy of spinal cord compression measurement in a mouse contusion model’, J. Neurosci. Methods, 2018, 293, pp. 15.
    12. 12)
      • 7. Ahmad, A., Krill, B., Amira, A., et al: ‘Efficient architectures for 3D HWT using dynamic partial reconfiguration’, J. Syst. Archit., 2010, 56, (8), pp. 305316.
    13. 13)
      • 9. Srinivasarao, B.K.N., Chakrabarti, I.: ‘High performance VLSI architecture for 3-D discrete wavelet transform’. IEEE Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2016, pp. 14.
    14. 14)
      • 5. Weeks, M., Bayoumi, M.: ‘3D discrete wavelet transform architectures’. IEEE Int. Symp. on Circuits and Systems, Monterey, California, USA, June 1998, pp. 5760.
    15. 15)
      • 18. Basiri, M.M.A., Sk, N.M.: ‘An efficient hardware based higher radix floating point MAC design’, ACM Trans. Des. Autom. Electron. Syst. (TODAES), 2014, 20, (1), pp. 15:115:25.
    16. 16)
      • 22. Teruyuki Miyoshi, M.D., Hironori Yoshida, M.D.: ‘Ultra-high-speed digital video images of vibrations of an ultrasonic tip and phacoemulsification’, J. Cataract Refract. Surg., 2008, 34, (6), pp. 10241028.
    17. 17)
      • 13. Das, A., Hazra, A., Banerjee, S.: ‘An efficient architecture for 3-D discrete wavelet transform’, IEEE Trans. Circuits Syst. Video Technol., 2010, 20, (2), pp. 286296.
    18. 18)
      • 15. Darji, A., Shukla, S., Merchant, S.N., et al: ‘Hardware efficient VLSI architecture for 3-D discrete wavelet transform’. 27th IEEE Int. Conf. on VLSI Design and 13th Int. Conf. on Embedded Systems, Mumbai, India, January 2014, pp. 348352.
    19. 19)
      • 3. Daubechies, I.: ‘The wavelet transform, time-frequency localization and signal analysis’, IEEE Trans. Inf. Theory, 1990, 36, (5), pp. 9611005.
    20. 20)
      • 1. DeVore, R.A., Jawerth, B., Lucier, B.J.: ‘Image compression through wavelet transform coding’, IEEE Trans. Inf. Theory, 1992, 38, (2), pp. 719746.
    21. 21)
      • 8. Jarrah, A., Jamali, M.M.: ‘Optimized FPGA based implementation of discrete wavelet transform’. 48th Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, USA, November 2014, pp. 18391842.
    22. 22)
      • 21. Shu, X., Wu, X.: ‘Real-time high-fidelity compression for extremely high frame rate video cameras’, IEEE Trans. Comput. Imaging, 2018, 4, (1), pp. 172180.
    23. 23)
      • 17. Hegde, G., Reddy, K.S., Ramesh, T.K.: ‘An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture’. 7th IEEE Int. Symp. on Embedded Computing and System Design (ISED), Durgapur, West Bengal, India, December 2017, pp. 15.
    24. 24)
      • 10. Al-Azawi, S., Abbas, Y.A., Jidin, R.: ‘Low complexity multidimensional CDF 5/3 DWT architecture’. 9th IEEE Int. Symp. on Communication Systems, Networks & Digital Sign (CSNDSP), Manchester, UK, July 2014, pp. 804808.
    25. 25)
      • 23. Eseholi, T., Notta-Cuvier, D., Coudoux, F-X., et al: Performance evaluation of strain field measurement by digital image correlation using HEVC compressed ultra-high speed video sequences’. IEEE Int. Symp. on Signal, Image, Video and Communications (ISIVC), Tunis, Tunisia, November 2016, pp. 142147.
    26. 26)
      • 11. Das, B., Banerjee, S.: ‘Data-folded architecture for running 3D DWT using 4-tap Daubechies filters’, IEE Circuits Devices Syst., 2005, 152, (1), pp. 1724.
    27. 27)
      • 19. Murofushi, T., Dobashi, T., Iwahashi, M., et al: ‘An integer tone mapping operation for HDR images in OpenEXR with denormalized numbers’. IEEE Int. Conf. on Image Processing (ICIP), Paris, France, October 2014, pp. 44974501.

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