Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

References

    1. 1)
      • 21. Kang, Y., Kim, J., Kim, S., et al: ‘A novel ternary multiplier based on ternary CMOS compact model’. IEEE 47th Int. Symp. Multiple-Valued Logic, Novi Sad, Serbia, May 2017, pp. 2530.
    2. 2)
      • 37. Stanford University CNFET Model website, 2008, Available at https://nano.stanford.edu/model.php.
    3. 3)
      • 7. Moaiyeri, M.H., Doostaregan, A., Navi, K.: ‘Design of energy-efficient and robust ternary circuits for nanotechnology’, IET Circuits Devices Syst., 2011, 5, (4), pp. 285296.
    4. 4)
      • 11. Liang, J., Chen, L., Jan, J., et al: ‘Design and evaluation of multiple valued logic gates using pseudo n-type carbon nanotube FETs’, IEEE Trans. Nanotechnol., 2014, 13, (4), pp. 695708.
    5. 5)
      • 36. Darvish, E., Mirzaee, R.F.: ‘Effective realization of ternary logic circuits by adapted map minimization method’. 8th Int. Conf. Computer and Knowledge Engineering, Mashhad, Iran, October 2018, pp. 211217.
    6. 6)
      • 8. Mirzaee, R.F., Nikoubin, T., Navi, K., et al: ‘Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic’, Microelectron. J., 2013, 44, (12), pp. 12381250.
    7. 7)
      • 14. Chu, K.M., Pulfrey, D.L.: ‘A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic’, IEEE J. Solid-State Circuits, 1987, 22, (4), pp. 528532.
    8. 8)
      • 33. Sharma, T., Kumre, L.: ‘CNTFET-based design of ternary arithmetic modules’, Circuits Syst. Signal Process., 2019, 38, (10), pp. 46404666.
    9. 9)
      • 20. Sahoo, S.K., Akhilesh, G., Sahoo, R., et al: ‘High performance ternary adder using CNTFET’, IEEE Trans. Nanotechnol., 2017, 16, (3), pp. 368374.
    10. 10)
      • 9. Rezaie, S., Mirzaee, R.F., Navi, K., et al: ‘New dynamic ternary minimum and maximum circuits with reduced switching activity and without additional voltage sources’, Int. J. High Perform. Syst. Archit., 2015, 5, (3), pp. 153165.
    11. 11)
      • 1. Karkar, A., Mak, T., Tong, K.F., et al: ‘A survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores’, IEEE Circuits Syst. Mag., 2016, 16, (1), pp. 5872.
    12. 12)
      • 12. Rabaey, J.M., Chandrakasan, A.P., Nikolic, B.: ‘Digital integrated circuits: a design perspective’ (Pearson Education, USA., 2003, 2nd Edn.).
    13. 13)
      • 39. Shams, A.M., Bayoumi, M.A.: ‘A novel high-performance CMOS 1-bit full-adder cell’, IEEE Trans. Circuits Syst. II, 2000, 47, (5), pp. 478481.
    14. 14)
      • 17. Moaiyeri, M.H., Shamohammadi, M., Sharifi, F., et al: ‘High-performance ternary logic gates for nanoelectronics’, Int. J. High Perform. Syst. Archit., 2015, 5, (4), pp. 209215.
    15. 15)
      • 18. Samadi, H., Shahhoseini, A., Aghaei-liavali, F.: ‘A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits’, Microelectron. J., 2017, 63, pp. 4148.
    16. 16)
      • 5. Rakos, B.: ‘Multiple-valued computing by dipole-dipole coupled proteins’, Int. J. Circuit Theory Appl., 2019, 47, (8), pp. 13571369.
    17. 17)
      • 28. Appenzeller, J.: ‘Carbon nanotubes for high-performance electronics-progress and prospect’, Proc. IEEE, 2008, 96, (2), pp. 201211.
    18. 18)
      • 27. Kim, Y.-B.: ‘Challenges for nanoscale MOSFETs and emerging nanoelectronics’, Tran. Electr. Electron. Mater., 2010, 11, (3), pp. 93105.
    19. 19)
      • 43. Wey, I.C., Chang, C.W., Liao, Y.C., et al: ‘Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique’, Int. J. Circuit Theory Appl., 2015, 43, (7), pp. 854865.
    20. 20)
      • 26. Martel, R., Schmidt, T., Shea, H.R., et al: ‘Single- and multi-wall carbon nanotube field-effect transistors’, Appl. Phys. Lett., 1998, 73, (17), pp. 24472449.
    21. 21)
      • 6. Lin, S., Kim, Y.-B., Lombardi, F.: ‘CNTFET-based design of ternary logic gates and arithmetic circuits’, IEEE Trans. Nanotechnol., 2011, 10, (2), pp. 217225.
    22. 22)
      • 30. Deng, J.: ‘Device modeling and circuit performance evaluation for nanoscale devices: Silicon technology beyond 45 nm node and carbon nanotube field effect transistors’. Ph.D. Dissertation, Stanford University, 2007.
    23. 23)
      • 4. Gaudet, V.: ‘A survey and tutorial on contemporary aspects of multiple-valued logic and its application to icroelectronic circuits’, IEEE J. Emerg. Sel. Top. Circuits Syst., 2016, 6, (1), pp. 512.
    24. 24)
      • 44. Takbiri, M., Mirzaee, R.F., Navi, K.: ‘Analytical review of noise margin in MVL: clarification of a deceptive matter’, Circuits Syst. Signal Process., 2019, 38, (9), pp. 42804301.
    25. 25)
      • 23. Kang, D.W., Kim, Y.-B.: ‘Design of enhanced differential cascode voltage switch logic (EDCVSL) circuits for high fan-in gate’. 15th Annual IEEE Int. ASIC/SOC Conf., Rochester, USA, September 2002, pp. 309313.
    26. 26)
      • 19. Tabrizchi, S., Sharifi, F., Badawy, A.H., et al: ‘Enabling energy-efficient ternary logic gates using CNFETs’. IEEE 17th Int. Conf. Nanotechnology, Pittsburgh, USA, July 2017, pp. 542547.
    27. 27)
      • 25. Nikoubin, T., Grailoo, M., Li, C.: ‘Energy and area efficient three-input XOR/XNORs with systematic cell design methodology’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24, (1), pp. 398402.
    28. 28)
      • 16. Wu, C.Y., Huang, H.Y.: ‘Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic’, IEEE J. Solid-State Circuits, 1993, 28, (8), pp. 895906.
    29. 29)
      • 3. Ganguly, A., Ahmed, M.M., Narde, R.S., et al: ‘The advances, challenges and future possibilities of millimetre-wave chip-to-chip interconnections for multi-chip systems’, J. Low Power Electron. Appl., 2018, 8, (1), pp. 136.
    30. 30)
      • 10. Jaber, R.A., Kassem, A., El-Hajj, A.M., et al: ‘High-performance and energy-efficient CNFET-based designs for ternary logic circuits’, IEEE Access, 2019, 7, pp. 9387193886.
    31. 31)
      • 34. Firouzi, S., Tabrizchi, S., Sharifi, F., et al: ‘High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design’, Comput. Electr. Eng., 2019, 77, pp. 205216.
    32. 32)
      • 40. Chang, C.H., Gu, J., Zhang, M.: ‘A review of 0.18-μm full adder performance for tree structured arithmetic circuits’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2005, 13, (6), pp. 686695.
    33. 33)
      • 22. Shahangian, M., Hosseini, S.A., Komleh, S.H.P.: ‘Design of a multi-digit binary-to-ternary converter based on CNTFETs’, Circuits Syst. Signal Process., 2019, 38, (6), pp. 25442563.
    34. 34)
      • 29. Rahman, A., Guo, L., Datta, S., et al: ‘Theory of ballistic nanotransistors’, IEEE Trans. Electron Devices, 2003, 50, (9), pp. 18531864.
    35. 35)
      • 24. Shams, A.M., Darwish, T.K., Bayoumi, M.A.: ‘Performance analysis of low-power 1-bit CMOS full adder cells’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2002, 10, (1), pp. 2029.
    36. 36)
      • 13. Rennels, D.A., Kim, H.: ‘Concurrent error detection in self-timed VLSI’. Proc. IEEE 24th Int. Symp. Fault-Tolerant Computing, Austin, USA, June 1994, pp. 96105.
    37. 37)
      • 38. Mishra, S., Singh, N.K., Rousseau, V.: ‘System on chip interfaces for low power design’ (Elsevier, USA., 2016, 1st Edn.).
    38. 38)
      • 41. Katopis, G.A.: ‘Delta-I noise specification for a high-performance computing machine’, Proc. IEEE, 1985, 73, (9), pp. 14051415.
    39. 39)
      • 15. Lakshmikanthan, P., Nunez, A.: ‘A novel methodology to reduce leakage power in differential cascode voltage switch logic circuits’. 3rd Int. Conf. Electrical and Electronics Engineering, Veracruz, Mexico, September 2006, pp. 14.
    40. 40)
      • 2. Achballah, A.B., Othman, S.B., Saoud, S.B.: ‘Problems and challenges of emerging technology networks-on-chip: a review’, Microprocess. Microsyst., 2017, 53, pp. 120.
    41. 41)
      • 31. Inokawa, H., Fujiwara, A., Takahashi, Y.: ‘A multiple-valued logic with merged single-electron and MOS transistors’. Int. Electron Devices Meeting, Washington, USA, December 2001, pp. 7.2.17.2.4.
    42. 42)
      • 32. Shahrom, E., Hosseini, S.A.: ‘A new low power multiplexer based ternary multiplier using CNTFETs’, AEU Int. J. Electron. Commun., 2018, 93, pp. 191207.
    43. 43)
      • 35. Soliman, N.S., Fouda, M.E., Radwan, A.G.: ‘Memristor-CNTFET based ternary logic gates’, Microelectron. J., 2018, 72, pp. 7485.
    44. 44)
      • 42. Simovich, S., Franzon, P., Steer, M.: ‘A simple method for noise tolerance characterization of digital circuits’. 3rd Great Lakes Symp. VLSI-Design Automation of High Performance VLSI Systems, Klamazoo, USA, March 1993, pp. 5256.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2019.0216
Loading

Related content

content/journals/10.1049/iet-cdt.2019.0216
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address